Abstract: A communication circuit includes a first buffer configured to output a signal indicative of a first logic state or a second logic state, a signal in which the first logic state and the second logic state are defined being input to the first buffer, a second buffer configured to output a signal indicative of any one of the first logic state, the second logic state, and a third logic state, the signal output from the first buffer being input to the second buffer, and a monitoring circuit configured to monitor a logic state indicated by the signal output from the first buffer and cause the second buffer, in a case where the logic state does not change during a first period, to output the signal indicative of the third logic state.

Abstract: A communication circuit includes a first buffer configured to output a signal indicative of a first logic state or a second logic state, a signal in which the first logic state and the second logic state are defined being input to the first buffer, a second buffer configured to output a signal indicative of any one of the first logic state, the second logic state, and a third logic state, the signal output from the first buffer being input to the second buffer, and a monitoring circuit configured to monitor a logic state indicated by the signal output from the first buffer and cause the second buffer, in a case where the logic state does not change during a first period, to output the signal indicative of the third logic state.

Abstract: A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal.

Abstract: A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal.

Abstract: An interface circuit inputting and outputting data and a clock that have multiple speeds is provided with an equalizer capable of changing a circuit parameter, a frequency detection part detecting a clock frequency, and a parameter calculation control part calculating an appropriate circuit parameter according to the clock frequency and controlling the equalizer. The frequency detection part detects at what frequency the interface circuit is operating presently and sends the frequency to the parameter calculation control part. The parameter calculation control part calculates the circuit parameter of the equalizer so that the interface circuit operates optimally at the detected frequency, and sets the circuit parameter to the equalizer. In this manner, since the circuit parameter of the equalizer in the interface circuit can be controlled appropriately according to the frequency of the input and output clock, optimum operation is always available.

Abstract: An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

Abstract: An interface circuit inputting and outputting data and a clock that have multiple speeds is provided with an equalizer capable of changing a circuit parameter, a frequency detection part detecting a clock frequency, and a parameter calculation control part calculating an appropriate circuit parameter according to the clock frequency and controlling the equalizer. The frequency detection part detects at what frequency the interface circuit is operating presently and sends the frequency to the parameter calculation control part. The parameter calculation control part calculates the circuit parameter of the equalizer so that the interface circuit operates optimally at the detected frequency, and sets the circuit parameter to the equalizer. In this manner, since the circuit parameter of the equalizer in the interface circuit can be controlled appropriately according to the frequency of the input and output clock, optimum operation is always available.

Abstract: A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal and the parallel data. The load circuit and the plurality of switching elements are connected in series between a first power source line and a second power source line. Each of the switching elements is controlled in accordance with an output of the logic circuit.

Abstract: A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal and the parallel data. The load circuit and the plurality of switching elements are connected in series between a first power source line and a second power source line. Each of the switching elements is controlled in accordance with an output of the logic circuit.