Abstract: In an unauthorized access information collection system for monitoring unauthorized access to a honeynet so as to collect unauthorized access information, the system includes: a plurality of honey pots in which a private address or a global address is respectively set and which construct the honeynet; and an unauthorized access information collection device which is disposed between an Internet and the honeynet and which allocates a plurality of global addresses to the private address or the global address by setting of a routing table to transfer a received packet and which performs a communication control from the honeynet side to the Internet side based on a communication control list and records the packets passing through the unauthorized access information collection device.

Abstract: An improper communication detection system that acquires packets that are circulated through a plant network by mirroring and detects improper communication includes a storage unit configured to prestore a session whitelist, which is a list of sessions that can be generated in the plant network; a session determination/separation unit configured to make a determination as to a success or failure of session approval on the basis of the acquired packet and configured to generate session information indicating an approved session; and a first improper communication detection unit configured to compare the session information generated by the session determination/separation unit with the session whitelist, and configured to detect communication related to the relevant session as improper communication when the session information does not match any session in the session whitelist.

Abstract: In an unauthorized access information collection system for monitoring unauthorized access to a honeynet so as to collect unauthorized access information, the system includes: a plurality of honey pots in which a private address or a global address is respectively set and which construct the honeynet; and an unauthorized access information collection device which is disposed between an Internet and the honeynet and which allocates a plurality of global addresses to the private address or the global address by setting of a routing table to transfer a received packet and which performs a communication control from the honeynet side to the Internet side based on a communication control list and records the packets passing through the unauthorized access information collection device.

Abstract: Efficient and high-accuracy parameter adjustment is performed by applying a genetic algorithm to a parameter adjustment such as a physical model of a transistor and so on. A parameter adjusting device includes a device generating new parameter genes by an initial population generating device and a special crossover processing by a Latin hyper square method. Also, a normalization device is provided for applying to parameters which are real numbers. Moreover, for example, to exactly meet a specific property of the transistor (MOSFET), an evaluation device which evaluates a parameter in consideration of a log scale, is provided. According to the above-mentioned structure, the genetic algorithm can be applied to the parameter adjustment with a large number of parameters such as the physical model of the transistor and so on, so that a parameter group can be determined with a high degree of accuracy within a short time.

Abstract: An enhancement mode field effect transistor whose operation threshold value varies greatly according to the substrate voltage. This field effect transistor is implemented by substituting the gate electrode of a depression mode field effect transistor for a gate electrode of the conductivity type opposite to that of a channel formation region, or a midgap gate electrode. In a preferred embodiment of the present invention, this field effect transistor is provided between a CMOS structure logic gate and a ground line. As a result, the leak current when the field effect transistor is not operating can be diminished without reducing the operational speed of the logic gate.

Abstract: A packet analysis system captures packets propagating through a network, and analyzes the captured packets. The packet analysis has a plurality of terminal node type sensors and a server. Each of the terminal node type sensors captures packets propagating through the network, and classifies the captured packets. A server acquires classification information from at least one of the terminal node type sensors through the network, and generates a whole report of the packet analysis system based the acquired classification information.

Abstract: An optimization method for extracting a model parameter in a semiconductor circuit. A fitness function circuit 15 installed in a genetic algorithm machine 900 is provided with an evaluated value calculation section 21, which receives an offspring model parameter from an offspring model parameter file 44, obtains k model evaluated values based on the offspring model parameter received, and stores the k model evaluated values in an evaluated value file 32 in a storage section 17. The fitness function circuit 15 is also provided with an area calculation section 22, which reads the k model evaluated values stored in the evaluated value file 32 by the evaluated value calculation section 21, calculates the size of an area formed by the k model evaluated values read, and stores the size of the area in an area value file 33 in the storage section 17.

Abstract: An enhancement mode field effect transistor whose operation threshold value varies greatly according to the substrate voltage. This field effect transistor is implemented by substituting the gate electrode of a depression mode field effect transistor for a gate electrode of the conductivity type opposite to that of a channel formation region, or a midgap gate electrode. In a preferred embodiment of the present invention, this field effect transistor is provided between a CMOS structure logic gate and a ground line. As a result, the leak current when the field effect transistor is not operating can be diminished without reducing the operational speed of the logic gate.

Abstract: In order to apply a predetermined voltage to a silicon layer (3) to control a threshold voltage, a second gate electrode (5) is provided on the surface of the silicon layer (3) with a gate oxide film (insulating layer) (4) interposed therebetween so as to fall within the same surface of the silicon layer (3) as a surface on which a source (7) and a drain (8) placed in the silicon layer (3) and a first gate electrode (6) are disposed.

Abstract: In order to apply a predetermined voltage to a silicon layer (3) to thereby control a threshold voltage, a second gate electrode (5) is provided on the surface of the silicon layer (3) with a gate oxide film (insulating layer) (4) interposed therebetween so as to fall within the same surface of the silicon layer (3) as a surface on which a source (7) and a drain (8) placed in the silicon layer (3) and a first gate electrode (6) are disposed.

Abstract: A semiconductor device includes a source and a drain formed in a device region of a semiconductor substrate, and an electrode withdrawal portion having an impurity concentration higher than that of the device region. The electrode withdrawal portion is formed so as to adjoin either one of the source and drain. An electrode for the source or drain adjacent to the electrode withdrawal portion is used jointly as an electrode for the electrode withdrawal portion.