Patents by Inventor Shunsuke HAZUE
Shunsuke HAZUE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11849579Abstract: A semiconductor storage device includes a stacked portion including an insulating layer and a conductor layer that are alternately stacked, and a plurality of memory pillars extending into the stacked portion. When viewed along a direction perpendicular to a surface of the stacked portion, the stacked portion includes a first area in which the plurality of memory pillars are provided, and a second area adjacent to the first area and free of the memory pillars. The first memory pillar of the plurality of memory pillars formed at a position closest to a boundary between the first area and the second area and a second memory pillar of the plurality of memory pillars that is adjacent to the first memory pillar have the same width.Type: GrantFiled: March 3, 2021Date of Patent: December 19, 2023Assignee: KIOXIA CORPORATIONInventor: Shunsuke Hazue
-
Publication number: 20220045085Abstract: A semiconductor storage device includes a stacked portion including an insulating layer and a conductor layer that are alternately stacked, and a plurality of memory pillars extending into the stacked portion. When viewed along a direction perpendicular to a surface of the stacked portion, the stacked portion includes a first area in which the plurality of memory pillars are provided, and a second area adjacent to the first area and free of the memory pillars. The first memory pillar of the plurality of memory pillars formed at a position closest to a boundary between the first area and the second area and a second memory pillar of the plurality of memory pillars that is adjacent to the first memory pillar have the same width.Type: ApplicationFiled: March 3, 2021Publication date: February 10, 2022Inventor: Shunsuke HAZUE
-
Patent number: 11049875Abstract: A semiconductor memory device according to embodiments described herein, includes a first stacked body, a second stacked body, a first memory hole, a second memory hole, and a joint. In the first stacked body, a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked. The second stacked body is disposed above the first stacked body, and a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked therein. The first memory hole extends in the first stacked body in a first direction that is a stacking direction of the first stacked body. The second memory hole extends in the second stacked body in the first direction. The joint communicates the first memory hole and the second memory hole. The joint includes an inner wall surface and a sidewall insulating layer. The inner wall surface has a plane continuous with the inner wall of the first memory hole.Type: GrantFiled: March 12, 2020Date of Patent: June 29, 2021Assignee: Kioxia CorporationInventor: Shunsuke Hazue
-
Publication number: 20210043646Abstract: A semiconductor memory device according to embodiments described herein, includes a first stacked body, a second stacked body, a first memory hole, a second memory hole, and a joint. In the first stacked body, a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked. The second stacked body is disposed above the first stacked body, and a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked therein. The first memory hole extends in the first stacked body in a first direction that is a stacking direction of the first stacked body. The second memory hole extends in the second stacked body in the first direction. The joint communicates the first memory hole and the second memory hole. The joint includes an inner wall surface and a sidewall insulating layer. The inner wall surface has a plane continuous with the inner wall of the first memory hole.Type: ApplicationFiled: March 12, 2020Publication date: February 11, 2021Applicant: Kioxia CorporationInventor: Shunsuke HAZUE
-
Patent number: 10818686Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first conductive layer arranged above the substrate; a stacked body arranged on the first conductive layer with a plurality of dielectric layers and a plurality of second conductive layers being alternately stacked; a pillar-shaped channel extending in a stacking direction of the stacked body, penetrating through the stacked body, and protruding into the first conductive layer; and a memory layer covering a side surface of the channel, in which a bottom surface of the channel and the side surface of the channel protruding into the first conductive layer are in contact with the first conductive layer, and in which the first conductive layer includes: an upper layer; and a lower layer having a protrusion penetrating through the upper layer.Type: GrantFiled: March 8, 2019Date of Patent: October 27, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shunsuke Hazue
-
Publication number: 20200075619Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first conductive layer arranged above the substrate; a stacked body arranged on the first conductive layer with a plurality of dielectric layers and a plurality of second conductive layers being alternately stacked; a pillar-shaped channel extending in a stacking direction of the stacked body, penetrating through the stacked body, and protruding into the first conductive layer; and a memory layer covering a side surface of the channel, in which a bottom surface of the channel and the side surface of the channel protruding into the first conductive layer are in contact with the first conductive layer, and in which the first conductive layer includes: an upper layer; and a lower layer having a protrusion penetrating through the upper layer.Type: ApplicationFiled: March 8, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Shunsuke HAZUE
-
Patent number: 9929041Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the foundation layer, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The plurality of electrode layers of the second stacked portion has a plurality of terrace portions arranged in a staircase configuration by forming a level difference in a first direction. The insulating layer provides on the plurality of terrace portions, the insulating layer includes silicon oxide as a major component. The insulating layer includes an upper layer portion and a lower layer portion. An oxygen composition ratio of the upper layer portion is lower than an oxygen composition ratio of the lower layer portion.Type: GrantFiled: March 10, 2017Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shunsuke Hazue
-
Publication number: 20180076085Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the foundation layer, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The plurality of electrode layers of the second stacked portion has a plurality of terrace portions arranged in a staircase configuration by forming a level difference in a first direction. The insulating layer provides on the plurality of terrace portions, the insulating layer includes silicon oxide as a major component. The insulating layer includes an upper layer portion and a lower layer portion. An oxygen composition ratio of the upper layer portion is lower than an oxygen composition ratio of the lower layer portion.Type: ApplicationFiled: March 10, 2017Publication date: March 15, 2018Applicant: Toshiba Memory CorporationInventor: Shunsuke HAZUE
-
Patent number: 9741739Abstract: A semiconductor manufacturing method includes alternately stacking first films and second films to form a stack film. The method includes forming a plurality of recessed portions in a stack direction of the stack film at an interval in a first direction substantially perpendicular to the stack direction. The semiconductor manufacturing method includes forming third films in the recessed portions. The method includes forming a mask material on the stack film and the third films and diminishing the mask material to expose the stack film in a first range between an end of a stepped portion to be formed on the stack film and one of the third films and to position an end of the mask material on the third film. The method includes removing a predetermined number of layers of films from the stack film in the first range using the diminished mask material as a mask.Type: GrantFiled: September 14, 2016Date of Patent: August 22, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shunsuke Hazue
-
Publication number: 20170207237Abstract: A semiconductor manufacturing method includes alternately stacking first films and second films to form a stack film. The method includes forming a plurality of recessed portions in a stack direction of the stack film at an interval in a first direction substantially perpendicular to the stack direction. The semiconductor manufacturing method includes forming third films in the recessed portions. The method includes forming a mask material on the stack film and the third films and diminishing the mask material to expose the stack film in a first range between an end of a stepped portion to be formed on the stack film and one of the third films and to position an end of the mask material on the third film. The method includes removing a predetermined number of layers of films from the stack film in the first range using the diminished mask material as a mask.Type: ApplicationFiled: September 14, 2016Publication date: July 20, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Shunsuke HAZUE