Patents by Inventor Shunsuke OHYA

Shunsuke OHYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-dimensional memory device with peripheral circuit located over support pillar array and method of making thereof
    Patent number: 11641746
    Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 2, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shunsuke Ohya, Sadao Fukuno, Koichi Nakamura
  • THREE-DIMENSIONAL MEMORY DEVICE WITH PERIPHERAL CIRCUIT LOCATED OVER SUPPORT PILLAR ARRAY AND METHOD OF MAKING THEREOF
    Publication number: 20220271053
    Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Inventors: Shunsuke OHYA, Sadao FUKUNO, Koichi NAKAMURA