Abstract: A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.

Abstract: A method of testing a device under test (DUT) connected between first and second DUT nodes includes generating a set of control signals, and in response to the set of control signals, disconnecting a first voltage node from a first DUT node, connecting a second voltage node to the first DUT node, periodically connecting and disconnecting a third voltage node to and from the second DUT node at a predetermined frequency, disconnecting a fourth voltage node from the second DUT node when the third voltage node is connected to the second DUT node, and connecting the fourth voltage node to the second DUT node when the third voltage node is disconnected from the second DUT node. A circuit that performs the method is also disclosed.

Abstract: A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.

Abstract: A method of testing a device under test (DUT) connected between first and second DUT nodes includes generating a set of control signals, and in response to the set of control signals, disconnecting a first voltage node from a first DUT node, connecting a second voltage node to the first DUT node, periodically connecting and disconnecting a third voltage node to and from the second DUT node at a predetermined frequency, disconnecting a fourth voltage node from the second DUT node when the third voltage node is connected to the second DUT node, and connecting the fourth voltage node to the second DUT node when the third voltage node is disconnected from the second DUT node. A circuit that performs the method is also disclosed.

Abstract: A differential signal correction circuit is disclosed. The differential signal correction circuit may comprise a first single-ended-to-differential converter and a second single-ended-to-differential converter. Each one of the two converters may comprise an input port and two output ports. The converters may be configured to perform a first phase correction for a pair of differential signals and output a first output signal and a second output signal. The first output signal is fed back to the first converter through one of the output ports of the first converter, and the second output signal is fed back to the second converter through one of the output ports of the second converter so as to perform phase correction and amplitude correction for the first output signal and the second output signal.

Abstract: A differential signal correction circuit is disclosed. The differential signal correction circuit may comprise a first single-ended-to-differential converter and a second single-ended-to-differential converter. Each one of the two converters may comprise an input port and two output ports. The converters may be configured to perform a first phase correction for a pair of differential signals and output a first output signal and a second output signal. The first output signal is fed back to the first converter through one of the output ports of the first converter, and the second output signal is fed back to the second converter through one of the output ports of the second converter so as to perform phase correction and amplitude correction for the first output signal and the second output signal.