Abstract: A successive approximation register digital analog-to-digital converter, and an electronic device. The successive approximation register digital analog-to-digital converter comprises a positive capacitor array, a negative capacitor array, a switching circuit, a comparator and an SAR logic circuit, wherein the SAR logic circuit is configured to control the reference voltages to which the plurality of first capactiros are connected through the plurality of second capacitors are connected through the plurality of groups of second bottom plate switches according to each bit of digital signal outputted by the comparator.

Abstract: Provided are an oral solid tablet comprising (S)-7-[4-(1-acryloylpiperidine)]-2-(4-phenoxyphenyl)-4,5,6,7-tetrahydropyrazolo[1,5-a]pyrimidine-3-carboxamide and preparation method therefor. The oral solid tablet has good drug release characteristics, features easy administration, quick and high-efficient release, no particular requirements on equipment, and a simple formulation preparation process, can ensure formulation stability and facilitate transportation and storage, and is suitable for large-scale production.

Abstract: A dual purpose camera is provided. The dual purpose camera has a doccam mode and a webcam mode. The dual purpose camera includes a base, a supporting member, and a camera. The supporting member is detachably or rotatably coupled to the base. The camera is rotatably or detachably coupled to the supporting member. The camera rotates with respect to a reference plane of the dual purpose camera between a first position and a second position. When it is detected that the camera is attached to the base and the camera rotates from the first position to the second position, the camera automatically outputs a 180 degree rotated image.

Abstract: Provided is a capacitance detection circuit, which has better detection performance. The capacitance detection circuit includes: a first charging and discharging circuit configured to perform charging or discharging on a capacitor to be detected; a second charging and discharging circuit configured to perform charging or discharging on a calibration capacitor; an analog-to-digital conversion circuit configured to continuously sample a voltage difference between the capacitor to be detected and the calibration capacitor in a charging or discharging process to obtain sampled data; and a digital processing circuit configured to detect a capacitance of the capacitor to be detected according to the sampled data.

Abstract: A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.

Abstract: A capacitance detecting circuit, includes a first front end circuit, a second front end circuit, a control circuit and a processing circuit, wherein the control circuit controls the first front end circuit and the second front end circuit such that the first front end circuit is configured to convert a capacitance signal of a detection capacitor into a first voltage signal through a first calibration capacitor, and the second front end circuit is configured to convert a capacitance signal of the detection capacitor into a second voltage signal through a second calibration capacitor; the processing circuit is calculates a differential signal of the first voltage signal and the second voltage signal to determine a capacitance variation of the detection capacitor according to the differential signal.

Abstract: Provided is a capacitance detection circuit, which has better detection performance. The capacitance detection circuit includes: a first charging and discharging circuit configured to perform charging or discharging on a capacitor to be detected; a second charging and discharging circuit configured to perform charging or discharging on a calibration capacitor; an analog-to-digital conversion circuit configured to continuously sample a voltage difference between the capacitor to be detected and the calibration capacitor in a charging or discharging process to obtain sampled data; and a digital processing circuit configured to detect a capacitance of the capacitor to be detected according to the sampled data.

Abstract: A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.

Abstract: The present application discloses a capacitance detecting circuit, a touch device and terminal device, which are beneficial for reducing an area of the capacitance detecting circuit, thereby reducing costs of a chip. The capacitance detecting circuit is connected to a measurement capacitor and where it includes a calibration capacitor; a charging and discharging module including a first current source configured to perform charging or discharging on the measurement capacitor, and a second current source configured to perform charging or discharging on the calibration capacitor; an integrator, configured to convert a capacitance signal of the measurement capacitor into a voltage signal; and a control module, configured to control working states of the charging and discharging module and the integrator.

Abstract: A dynamic amplification circuit includes a first drive circuit (310) generates a first driving voltage according to a first control signal and a first driving current; a second drive circuit (320) generates a first driving signal according to the first and a second driving voltage; a third drive circuit (330) generates a second control signal according to the first control signal and the first driving signal; and a dynamic amplifier DA (340) includes a first branch (101) including a first capacitor and a second branch (102) including a second capacitor which are connected by a first resistor (150) and a second resistor (160), an operation state of the DA (340) is controlled through the first and second control signals, a duration of the DA (340) in an amplification phase is proportional to a product of a resistance value of the first resistor and a capacitance value of the first capacitor.

Abstract: The present disclosure discloses a dynamic amplification circuit, including: a first drive circuit, receives a first control signal to generate a first and a second voltage signal; a second drive circuit, receives the first and the second voltage signal to generate a first drive signal; a third drive circuit, receives the first control signal and the first drive signal to generate a second control signal; and a dynamic amplifier DA, controls a first and a second control switch according to the control signals; in a first time period, the first control signal is high level, the second control signal is low level; in a second time period, the opposite is the case; in a third time period, the first and the second control signal are both at low level, a duration of the second time period is inversely proportional to a transconductance of a transistor in a saturation region.