Abstract: A method for returning to a basic input/output system (BIOS) setup utility while in a shell environment during a booting process of a computing system includes: upon execution of an update Unified Extensible Firmware Interface (UEFI) (BIOS) firmware file, storing a dynamic command in a command storage; storing a back protocol in the storage module, the back protocol being linked to a back function that, when executed, causes the CPU to call a program file that, when executed by the CPU, causes the CPU to enter a BIOS setup utility, the dynamic command being linked to accessing a memory location in which the back protocol is stored; and in response to receipt of the dynamic command while in the shell environment, locating the back protocol, performing the back function and calling the specific program file, which causes the CPU to enter the BIOS setup utility.

Abstract: An operation method of a software program meeting UEFI specifications for configuring a GPIO port is provided. The operation method includes: operating in a command-line mode to display, on a display device, a first prompt for guiding a user to input a string of command-line arguments; in response to receipt of a string of command-line arguments for reading content stored in a register that corresponds to one of GPIO pins of the GPIO port under the command-line mode, displaying, on the display device, a default value of the register that corresponds to a function of said one of the GPIO pins; and in response to receipt of a string of command-line arguments for setting a register that corresponds to one of the GPIO pins to a set value under the command-line mode, writing the set value to the register to replace a current value with the set value.

Abstract: A radio frequency integrated circuit comprising: at least one transistor; a matching circuit coupled to said transistor; and at least one bump is used to form a passive element in said matching circuit, and said bump is used for radio frequency matching, the bumps can be used as passive components for amplifier harmonic impedance matching or the bumps can be the amplifier's passive components of the harmonic impedance matching, both of them can enhance the power, bandwidth and efficiency of amplifiers and integrated circuits.

Abstract: A program signing method is provided to include: determining whether the signing program is tampered with; if not, obtaining a releasing hash that is related to a to-be-released program, and transmitting the releasing hash to a signature server unit, so as to make the signature server unit acquire a releasing digital signature based on the releasing hash and transmit the releasing digital signature to the processing module; and, upon receipt of the releasing digital signature, executing the signing program to generate a signed to-be-released program.

Abstract: A method of collecting error logs according to the disclosure includes generating, during procedure of BIOS of a server, at least one BIOS error log based on detection of an error condition of one or more of hardware devices and a CPU, transmitting the at least one BIOS error log to a BMC, storing the at least one BIOS error log received from the CPU, packaging the at least one BIOS error log and at least one log that is generated by the BMC and that is related to BMC sensors to generate an error log file, and storing the error log file.

Abstract: A method of data management is to be implemented by a baseboard management controller (BMC) of a server. The method includes: collecting normal (abnormal) operation information that is related to current statuses of hardware and firmware components; selecting a portion of the normal (abnormal) operation information; classifying each piece of data included in the portion of the normal (abnormal) operation information as a hardware class or a firmware class; and storing the portion of the normal (abnormal) operation information in the storage.

Abstract: A method of collecting error logs according to the disclosure includes generating, during procedure of BIOS of a server, at least one BIOS error log based on detection of an error condition of one or more of hardware devices and a CPU, transmitting the at least one BIOS error log to a BMC, storing the at least one BIOS error log received from the CPU, packaging the at least one BIOS error log and at least one log that is generated by the BMC and that is related to BMC sensors to generate an error log file, and storing the error log file.

Abstract: A wideband impedance matching network comprises a fundamental output MN including a first portion and a second portion and a harmonic compensation MN including a harmonic MN portion and a harmonic MN backside-via inductor formed on an outer surface of a harmonic MN backside via hole penetrating through a semiconductor substrate. The first portion, the second portion and the harmonic MN portion are formed on the semiconductor substrate. A second terminal of the first portion and a first terminal of the second portion are connected to an RF output terminal. A first terminal of the harmonic MN portion and a first terminal of the first portion are connected to an RF input terminal. A second terminal of the harmonic MN portion is connected to a first terminal of the harmonic MN backside-via inductor. A second terminal of the harmonic MN backside-via inductor is grounded.

Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.

Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.

Abstract: A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 ?m and not greater than 4 ?m. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.

Abstract: A Schottky barrier diode includes a substrate, a buffer layer formed on the substrate, an upper layer formed on the buffer layer, a first electrode layer formed on the upper layer as an anode of the Schottky barrier diode, a second electrode layer formed on the upper layer as a cathode of the Schottky barrier diode, and a first n-type doping region formed in the upper layer and under the first electrode layer, and contacting the first electrode layer. An edge of the first n-type doping region and an edge of the first electrode layer are separated by a first predetermined distance at a first direction at which the first electrode layer faces the second electrode layer.

Abstract: A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 ?m and not greater than 4 ?m. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.

Abstract: A radio frequency (RF) power transistor includes: a semiconductor heterostructure that includes an undoped barrier layer and an active layer and that is formed with a continuous two dimensional electron gas (2DEG) channel having an ohmic source-aligned region, an ohmic drain-aligned region and a Schottky-aligned region; agate electrode; and source and drain electrodes. One of the source and drain electrodes includes an ohmic contact and a Schottky contact that extends from the ohmic contact toward the gate electrode. The 2DEG channel is normally on and extends continuously from the ohmic source-aligned region to the ohmic drain-aligned region. The Schottky contact overlaps and is capacitively coupled to the Schottky-aligned region of the 2DEG channel.

Abstract: A Schottky barrier diode includes a substrate, a buffer layer formed on the substrate, an upper layer formed on the buffer layer, a first electrode layer formed on the upper layer as an anode of the Schottky barrier diode, a second electrode layer formed on the upper layer as a cathode of the Schottky barrier diode, and a first n-type doping region formed in the upper layer and under the first electrode layer, and contacting the first electrode layer. An edge of the first n-type doping region and an edge of the first electrode layer are separated by a first predetermined distance at a first direction at which the first electrode layer faces the second electrode layer.

Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.

Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.

Abstract: A Schottky diode structure and a method for fabricating the same, which are based on the principle of charge compensation, wherein a P-type gallium nitride layer is added to a Schottky diode structure, and wherein the PN junction of the P-type gallium nitride layer and the N-type gallium nitride layer decreases the non-uniformity of the surface electric field distribution, whereby the breakdown voltage of the element is raised.

Abstract: A Schottky diode structure and a method for fabricating the same, which are based on the principle of charge compensation, wherein a P-type gallium nitride layer is added to a Schottky diode structure, and wherein the PN junction of the P-type gallium nitride layer and the N-type gallium nitride layer decreases the non-uniformity of the surface electric field distribution, whereby the breakdown voltage of the element is raised.

Abstract: The invention relates to an integrated circuit capable of repeatedly using current, the integrated circuit comprises: a first differential input, a first cross couple pair, a second differential input, a second cross couple pair, and a voltage-controlled oscillator, wherein a divider consists of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, moreover, through the connection of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, the divider and the voltage-controlled oscillator may be drove by only one single current, so that the circuit area, the power consumption, and the phase noise of the integrated circuit are simultaneously reduced.