Abstract: Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock.

Abstract: A test apparatus that tests a device under test having a plurality of blocks operating asynchronously, based on a signal received from outside, the test apparatus comprising a plurality of domain test units corresponding respectively to the blocks; and a main body unit that controls the domain test units. The main body unit includes a reference operation clock generating section that generates a reference operation clock supplied to each domain test unit, and a test start signal generating section that generates a test start signal instructing each domain test unit to start the testing. Each domain test unit includes a test clock generating section that generates a test clock based on the reference operation clock, and generates a test signal for testing the corresponding block based on the test clock obtained by the test clock generating section, and each domain test unit starts generating the test signal on a condition that the test start signal is received.

Abstract: Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock.

Abstract: A semiconductor test apparatus to test a semiconductor circuit includes a pattern generator which generates a test pattern for testing the semiconductor circuit, a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern, a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal and outputs the timing signal to the waveform shaper, and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit.

Abstract: A testing apparatus includes a logic comparing unit for comparing the output value with a predetermined expectation value; a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of the logic comparing unit; and a clock generating circuit including a first phase comparing unit for comparing phase of the output data of the device under test with that of the reproduced clock and outputting a first comparison result signal; a second phase comparing unit for comparing phase of the reference clock with that of the reproduced clock and outputting a second comparison result signal; and a reproduced clock generating module for generating the reproduced clock based on the first and second comparison result signals.

Abstract: A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current.

Abstract: There is provided a pulse width adjusting circuit for generating an output signal by adjusting a pulse width of an input pulse signal and outputting the output signal. The pulse width adjusting circuit includes a first delay circuit to output a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit to output a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section to generate and output the output signal in accordance with the first and second delay signals. Here, the output signal has a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits.

Abstract: A semiconductor test apparatus to test a semiconductor circuit includes a pattern generator which generates a test pattern for testing the semiconductor circuit, a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern, a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal and outputs the timing signal to the waveform shaper, and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit.

Abstract: There is provided a pulse width adjusting circuit for generating an output signal by adjusting a pulse width of an input pulse signal and outputting the output signal. The pulse width adjusting circuit includes a first delay circuit to output a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit to output a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section to generate and output the output signal in accordance with the first and second delay signals. Here, the output signal has a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits.

Abstract: A testing apparatus according to the present invention includes: a clock generating circuit for generating a reproduced clock of which frequency and phase are substantially the same as frequency of the reference clock and phase of output data of a device under test, respectively; a delay circuit for generating a strobe for delaying the reproduced clock; a timing comparator for obtaining an output value of the output data based on the strobe; a logic comparing unit for comparing the output value with a predetermined expectation value; and a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of the logic comparing unit, and the clock generating circuit includes: a first phase comparing unit for comparing phase of the output data of the device under test with that of the reproduced clock and outputting a first comparison result signal; a second phase comparing unit for comparing phase of the reference clock with that of the reproduced clock and outputti

Abstract: A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current.