Patents by Inventor Shutaro Nanbu

Shutaro Nanbu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a protection breakdown diode on a semi-insulative substrate
    Patent number: 4665416
    Abstract: A semiconductive device comprising a substrate of a semi-insulative material, a first impurity-doped semiconductive region of an n-conductivity type formed in the substrate, a second impurity-doped semiconductive region of p-conductivity type formed in the substrate. The second region has a generally U-shaped cross-section, one of the vertical limbs of the U adjoining the first region to form a p-n junction therewith and the web portion of the U being located in a position deeper than the bottom of the first region. First and second conductors are deposited on the first and second regions to provide an ohmic contact therewith.
    Type: Grant
    Filed: September 18, 1986
    Date of Patent: May 12, 1987
    Assignee: Matsushita Electronics Corporation
    Inventors: Masahiro Hagio, Shutaro Nanbu, Kunihiko Kanazawa, Shunji Ogata, Shiro Tohmori
  • Field effect transistor
    Patent number: 4459556
    Abstract: A dual gate Schottky barrier gate GaAs FET with improved cross-modulation characteristics when used in a UHF gain controlling tuner, having a value of 40 mA or smaller of a drain to source saturation current, the improvement of the FET is that length of a second gate which is disposed between a first gate and a drain is 1.5 .mu.m or longer.
    Type: Grant
    Filed: October 7, 1983
    Date of Patent: July 10, 1984
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shutaro Nanbu, Atsushi Nagashima, Gota Kano