Patents by Inventor Shuuichi Nagasawa

Shuuichi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7505310
    Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: March 17, 2009
    Assignee: NEC Corporation
    Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
  • Publication number: 20060255987
    Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.
    Type: Application
    Filed: March 14, 2006
    Publication date: November 16, 2006
    Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe