Patents by Inventor Shuuichi Tominaga

Shuuichi Tominaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7067874
    Abstract: A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench may extend from the main surface to the substrate and have an inner wall covered with an insulating film. At least one of an edge on the side of the substrate and an edge on the side opposite thereof of the semiconductor layer has a rounded surface. Further, an angle between a line tangent to a surface having a smallest radius of curvature of the rounded surface of the edge and the main surface ranges from 30° to 60° at a section of the edge.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: June 27, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Patent number: 6710401
    Abstract: A semiconductor device which includes a substrate made of a semiconductor having a main surface. A trench is selectively formed in the substrate at a predetermined depth from the main surface. An insulating film is formed at an inner wall of the trench. A control electrode layer fills an inside of the trench through the insulating film. An insulating layer protrudes from the main surface on the control electrode layer. At least one of an edge of an opening of the trench and a bottom of the trench has a rounded surface.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: March 23, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Publication number: 20030203573
    Abstract: There is disclosed a method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device. (FIG.
    Type: Application
    Filed: May 13, 2003
    Publication date: October 30, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Patent number: 6423598
    Abstract: A Schottky diode which provides a structure having no P-N junction while improving voltage resistance against a reverse bias when employed in combination with an insulated gate semiconductor device in particular. In order to attain the aforementioned object, a P-type impurity region having a surface exposed on a surface of an N-type semiconductor substrate functioning as a drain for functioning as a channel region and a gate insulator film covering it are provided. A gate electrode is extended from above the gate insulator film over a first taper of an oxide film. In a Schottky diode rendering the semiconductor substrate a cathode and having a boundary layer as a Schottky region, on the other hand, an anode electrode is extended from above the boundary layer over a second taper of the oxide film existing above an end portion of the boundary layer.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: July 23, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Takahashi, Shuuichi Tominaga
  • Publication number: 20010006836
    Abstract: There is disclosed a method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.
    Type: Application
    Filed: May 11, 2000
    Publication date: July 5, 2001
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Patent number: 5783491
    Abstract: A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: July 21, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Patent number: 5578522
    Abstract: A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X <5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X<5 permits a first main electrode to be formed nondefectively without being affected by the ground pattern including the insulating layers.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: November 26, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa