Abstract: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion.