Patents by Inventor Shyam AGARWAL
Shyam AGARWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11271011Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.Type: GrantFiled: July 9, 2020Date of Patent: March 8, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Shyam Agarwal, Abhishek Ghosh, Parvinder Kumar Rana
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Publication number: 20200343267Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.Type: ApplicationFiled: July 9, 2020Publication date: October 29, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Shyam AGARWAL, Abhishek GHOSH, Parvinder Kumar RANA
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Patent number: 10784864Abstract: According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.Type: GrantFiled: August 6, 2019Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Matthew Berzins, Lalitkumar Motagi, Shyam Agarwal
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Publication number: 20200295758Abstract: According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.Type: ApplicationFiled: August 6, 2019Publication date: September 17, 2020Inventors: Matthew BERZINS, Lalitkumar MOTAGI, Shyam AGARWAL
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Patent number: 10748932Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.Type: GrantFiled: September 7, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Shyam Agarwal, Abhishek Ghosh, Parvinder Kumar Rana
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Patent number: 10715118Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.Type: GrantFiled: August 13, 2018Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Shyam Agarwal, Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Kumar Ghosh, Parvinder Kumar Rana
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Publication number: 20200044631Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.Type: ApplicationFiled: October 5, 2018Publication date: February 6, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shyam AGARWAL, Sandeep B V, Sheetal Y KOCHREKAR, Abhishek GHOSH, Parvinder Kumar RANA, Rohit BISHT
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Publication number: 20190058461Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.Type: ApplicationFiled: August 13, 2018Publication date: February 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Shyam AGARWAL, Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Kumar Ghosh, Parvinder Kumar Rana
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Publication number: 20190006388Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.Type: ApplicationFiled: September 7, 2018Publication date: January 3, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Shyam Agarwal, Abhishek Ghosh, Parvinder Kumar Rana
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Patent number: 10103172Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.Type: GrantFiled: June 5, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Shyam Agarwal, Abhishek Ghosh, Parvinder Kumar Rana
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Publication number: 20180083036Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.Type: ApplicationFiled: June 5, 2017Publication date: March 22, 2018Applicant: Samsung Eletronics Co., Ltd.Inventors: Shyam AGARWAL, Abhishek Ghosh, Parvinder Kumar Rana