Abstract: A process is provided for etching thermally grown oxide. The process involves various steps and specific etch processing parameters used within a parallel electrode reactor. There are pre-stabilizing steps, followed by an etch step, which is then followed by post-stabilizing steps. The post-stabilizing steps may further include a particle removal or byproduct flush step in addition to the post-stabilizing steps. The process parameters are chosen to remove thermal oxide within contact regions at a uniform rate. The resulting thermal oxide is substantially uniform with less than 3.0% variance in thickness across the contact regions and across like areas of the entire wafer surface. The unique combination of pre-stabilize, etch, post-stabilize steps and process parameters chosen for each step thereby provides an improved etch uniformity of thermal oxide films within fine-line areas.

Abstract: A non-volatile memory device is provided having an array of single transistor memory cells read in accordance with an improved read cycle operation. That is, a selected cell mutually connected via a single bit line to other cells is assured activation necessary to discern a programmed or unprogrammed state of that cell. The non-selected cells connected to the selected cell are advantageously assured of non-activation by applying a negative voltage to the word lines associated with those cells. The negative voltage is less than the threshold voltage associated with the single transistor MOS device. The non-selected cells are thereby retained inactive to provide a singular active or inactive selected cell dependent solely upon the programmed state of the array. Negative voltage upon the non-selected cells provides minimal leakage of over-erased cells normally associated with depletion mode operation.

Abstract: An SOG plasma etch process is presented which is optimized for selectivity to PECVD silicon nitride. The present process also produces a uniform etch across the exposed surface of a semiconductor wafer. The etch process finds utility in dielectric-SOG-dielectric structures used as passivation layers. Silicon nitride is deposited using a PECVD technique to form the dielectric layers. By etching SOG at a faster rate than the rate at which it etches PECVD silicon nitride, the SOG plasma etch process removes enough of the SOG layer to prevent delamination problems associated with SOG layers interposed between dielectric layers without significantly reducing the thickness of the first dielectric layer. SOG remains only in troughs between closely-spaced interconnects and adjacent to the vertical steps between widely-spaced interconnects. Flow rates of He, CHF.sub.3, and N.sub.2 gases are established through a reaction chamber of a plasma etch system.

Abstract: A non-volatile memory device is provided having various electrical couplings for maximizing over-erased correction of that device. Over-erased devices within an array can be corrected in bulk, simultaneous with all other devices within the array. Bulk correction of an array of over-erased device is carried forth in a convergence technique which utilizes higher floating gate injection currents. Negatively biased substrate causes an enhancement in the injection current and resulting correction capability of the convergence operation. Moreover, convergence can be carried out with a lesser positive voltage upon the drain region, which implies a reduction in the source-to-drain currents as well as substrate currents during the convergence operation. Accordingly, only over-erased transistors receive sufficient turn-on during convergence, while all other transistors remain off.

Abstract: An MOS device is provided having a drain- or source-side implant into the channel region in order to minimize short-channel effects. Implant into the channel region is achieved using conventional processing techniques, wherein the channel implant is directed substantially perpendicular to the upper surface of the substrate. Numerous masking steps and reorientation of the substrate is not needed. Additionally, the drain- or source-side implant mask can be formed from currently existing masks and incorporated into a standard processing flow for either a standard MOS device or a memory array comprising dual-level polysilicon. If drain-side implant is chosen, then the lateral demarcation line between the drain implant and the substrate is preferably placed within the channel region, and preferably near a mid-point within the channel a spaced distance below a subsequently placed, overlying polysilicon.

Abstract: A flash EPROM device is provided for programmably storing digital data within a core array of electrically programmable transistors. A row or column within the array can be substituted for a spare or redundant row or column selectively connected to row or column decoder circuits by a redundancy select transistor. Self-aligned source regions within the array and redundancy select area are provided using a single mask for opening the self-aligned source regions and for implanting a light dosage of phosphorus directly into the underlying silicon substrate. Careful control and elimination of residue within the etched area via a subsequent wet etch helps ensure the implant edges are anisotropically controlled and isolated for subsequent lateral diffusion/drive-in. Accordingly, the flash EPROM device of a plurality of transistors within the array and within the redundancy select area are process controlled and demonstrate a significant reduction in threshold skewing.

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.