Patents by Inventor Shyamsunder BALASUBRAMANIAN
Shyamsunder BALASUBRAMANIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11888391Abstract: A device includes a charge pump configured to provide a current to a bootstrap capacitor responsive to a charge pump switch being closed. The device also includes a current limiter coupled in series between the charge pump switch and the charge pump. The current limiter is configured to receive a control signal from a controller that indicates whether the device is to operate in a first mode or in a second mode; responsive to the control signal indicating the first mode, allow a first value of current to the charge pump switch; and, responsive to the control signal indicating the second mode, limit the current to the charge pump switch to a second value. The second value is less than the first value.Type: GrantFiled: September 29, 2021Date of Patent: January 30, 2024Assignee: Texas Instruments IncorporatedInventors: Shyamsunder Balasubramanian, Kuangyu Chiang, Toshio Yamanaka, Luis Eduardo Ossa
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Patent number: 11764664Abstract: An example apparatus includes a level shifter having a first supply input, a gate driver having a second supply input coupled to the first supply input and adapted to be coupled to a cathode of a diode, the gate driver having an output adapted to be coupled to a control terminal of a switch, and a current source circuit having an input and an output, the input adapted to be coupled to a power supply and the output adapted to be coupled to the first supply input, the second supply input and to a capacitor.Type: GrantFiled: July 6, 2021Date of Patent: September 19, 2023Assignee: Texas Instruments IncorporatedInventors: Shyamsunder Balasubramanian, Michael Edwin Butenhoff, Toshio Yamanaka, Luis Eduardo Ossa
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Patent number: 11722126Abstract: A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.Type: GrantFiled: August 31, 2021Date of Patent: August 8, 2023Assignee: Texas Instruments IncorporatedInventors: Shyamsunder Balasubramanian, Michael Edwin Butenhoff, Toshio Yamanaka
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Publication number: 20230100060Abstract: A device includes a charge pump configured to provide a current to a bootstrap capacitor responsive to a charge pump switch being closed. The device also includes a current limiter coupled in series between the charge pump switch and the charge pump. The current limiter is configured to receive a control signal from a controller that indicates whether the device is to operate in a first mode or in a second mode; responsive to the control signal indicating the first mode, allow a first value of current to the charge pump switch; and, responsive to the control signal indicating the second mode, limit the current to the charge pump switch to a second value. The second value is less than the first value.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Shyamsunder BALASUBRAMANIAN, Kuangyu CHIANG, Toshio YAMANAKA, Luis Eduardo Ossa
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Publication number: 20230067055Abstract: A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Shyamsunder BALASUBRAMANIAN, Michael Edwin BUTENHOFF, Toshio YAMANAKA
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Publication number: 20230010450Abstract: An example apparatus includes a level shifter having a first supply input, a gate driver having a second supply input coupled to the first supply input and adapted to be coupled to a cathode of a diode, the gate driver having an output adapted to be coupled to a control terminal of a switch, and a current source circuit having an input and an output, the input adapted to be coupled to a power supply and the output adapted to be coupled to the first supply input, the second supply input and to a capacitor.Type: ApplicationFiled: July 6, 2021Publication date: January 12, 2023Inventors: Shyamsunder Balasubramanian, Michael Edwin Butenhoff, Toshio Yamanaka, Luis Eduardo Ossa
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Patent number: 11398799Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.Type: GrantFiled: December 3, 2019Date of Patent: July 26, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shyamsunder Balasubramanian, Wenxiao Tan, Mayank Garg, Toru Tanaka
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Patent number: 10700586Abstract: A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.Type: GrantFiled: April 29, 2016Date of Patent: June 30, 2020Assignee: Texas Instruments IncorporatedInventors: Shyamsunder Balasubramanian, Toshio Yamanaka, Toru Tanaka, Mayank Garg
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Publication number: 20200106396Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Inventors: Shyamsunder BALASUBRAMANIAN, Wenxiao TAN, Mayank GARG, Toru TANAKA
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Patent number: 10530308Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.Type: GrantFiled: March 23, 2018Date of Patent: January 7, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shyamsunder Balasubramanian, Wenxiao Tan, Mayank Garg, Toru Tanaka
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Publication number: 20190296695Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: Shyamsunder BALASUBRAMANIAN, Wenxiao TAN, Mayank GARG, Toru TANAKA
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Patent number: 10291163Abstract: A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.Type: GrantFiled: April 29, 2016Date of Patent: May 14, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Alejandro Vera, Shyamsunder Balasubramanian, Toshio Yamanaka, Toru Tanaka
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Patent number: 9985571Abstract: An apparatus includes a control circuit that includes a configuration register and configured to receive a configuration setting across an external bus. The configuration setting encodes a first voltage state for the apparatus. The control circuit includes an input configured to be coupled to an external electrical device. The control circuit is configured to determine a value of the external device that maps to a second voltage state for the apparatus. The control logic is configured to transition the apparatus to a safe mode upon a determination that the first voltage state does not match the second voltage state.Type: GrantFiled: April 29, 2016Date of Patent: May 29, 2018Assignee: Texas Instruments IncorporatedInventors: Toshio Yamanaka, Shyamsunder Balasubramanian, Toru Tanaka, Mayank Garg
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Publication number: 20170317619Abstract: A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Shyamsunder BALASUBRAMANIAN, Toshio YAMANAKA, Toru TANAKA, Mayank GARG
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Publication number: 20170317625Abstract: A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Alejandro VERA, Shyamsunder BALASUBRAMANIAN, Toshio YAMANAKA, Toru TANAKA
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Publication number: 20170317638Abstract: An apparatus includes a control circuit that includes a configuration register and configured to receive a configuration setting across an external bus. The configuration setting encodes a first voltage state for the apparatus. The control circuit includes an input configured to be coupled to an external electrical device. The control circuit is configured to determine a value of the external device that maps to a second voltage state for the apparatus. The control logic is configured to transition the apparatus to a safe mode upon a determination that the first voltage state does not match the second voltage state.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Toshio YAMANAKA, Shyamsunder BALASUBRAMANIAN, Toru TANAKA, Mayank GARG