Abstract: A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality of metal line patterns. The polysilicon layer disposed between the substrate and the metal layer includes a gate pattern and at least one guard ring pattern. The at least one guard ring pattern connects to the gate pattern and surrounds at least one of the metal line patterns. One of the metal line patterns connects to the gate pattern. The others of the metal line patterns connect to one of the doped regions in the substrate.

Abstract: A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d1. The shortest distance from a third side of each first or second active region to an extension line of each second side of the field implant region is d2. R=d1/d2, where 0.15?R?0.85. A gate structure covers the channel active region and extends over a portion of the isolation structure. Source/drain doped regions are formed in the first and the second active regions.

Abstract: A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality of metal line patterns. The polysilicon layer disposed between the substrate and the metal layer includes a gate pattern and at least one guard ring pattern. The at least one guard ring pattern connects to the gate pattern and surrounds at least one of the metal line patterns. One of the metal line patterns connects to the gate pattern. The others of the metal line patterns connect to one of the doped regions in the substrate.

Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Abstract: A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d1. The shortest distance from a third side of each first or second active region to an extension line of each second side of the field implant region is d2. R=d1/d2, where 0.15?R?0.85. A gate structure covers the channel active region and extends over a portion of the isolation structure. Source/drain doped regions are formed in the first and the second active regions.

Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Abstract: The invention is directed to a method for manufacturing an interconnect structure suitable for a substrate having a semiconductor device formed thereon, wherein the semiconductor device possesses a metal silicide layer predetermined as an electrically connecting region. The method comprises steps of forming a conformal adhesion layer over the substrate, forming a dielectric layer on the conformal adhesion layer and then performing a chemical mechanical polishing process to planarize the dielectric layer. Further, an opening penetrating through the dielectric layer and the conformal adhesion layer is formed, wherein the opening exposes a portion of the metal silicide layer. A conductive plug is formed in the opening.

Abstract: Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.

Abstract: A method for forming vias between a multi-layer structure and an interconnect is disclosed. The method is practiced on a semiconductor substrate having a conductive region and a multi-layer structure which has a first conductive layer on top. A retardation layer is formed over the first conductive layer and a dielectric layer is formed over the entire surface of the multi-layer structure, the entire surface of the conductive region and over the surface of the substrate. A first via hole is formed through both the dielectric layer and the retardation layer to expose a portion of the first conductive layer. A second via hole is formed through the dielectric layer to expose a portion of the conductive region. A first via plug is formed in the first via hole to electrically contact the first conductive layer and a second via plug is formed in the second via hole to electrically contact the conductive region.