Patents by Inventor Shyh An Chi
Shyh An Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130120021Abstract: An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shyh-An CHI
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Publication number: 20130106463Abstract: The embodiments described provide connection structures for dies in an integrated circuit die stack. Each die in the die stack includes a functional circuitry, a programmable array and a programmable array control unit. By triggering the programmable array control unit to program corresponding programmable array in each die of the die stack, signal routes are orchestrated to connect to corresponding functional circuitry in each die of the die stack to enable the entire die stack to meet functional goals. In addition, specific die(s) in the die stack may be bypassed by issuing control command to the programmable array control unit. Die(s) may be bypassed to meet functional goals and to improve yield, and reliability.Type: ApplicationFiled: November 15, 2011Publication date: May 2, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Shyh-An CHI
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Publication number: 20120319717Abstract: An apparatus comprises a die comprising a plurality of switch/router circuits; and a plurality of additional dies. Each respective one of the plurality of additional dies comprises: a respective network interface, which is electrically coupled to a respective one of the plurality of switch/router circuits; and a respective interconnection test logic, which is electrically coupled to the respective network interface and the interconnection test logic in at least one other one of the plurality of additional dies.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shyh-An CHI
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Publication number: 20120250286Abstract: A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shyh-An Chi, Mark Shane Peng
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Patent number: 8242826Abstract: A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.Type: GrantFiled: April 12, 2010Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee, Yun-Han Lee
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Publication number: 20120182650Abstract: Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.Type: ApplicationFiled: January 19, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Shyh-An Chi
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Publication number: 20120147567Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.Type: ApplicationFiled: December 9, 2010Publication date: June 14, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Han Lee, Mark Shane Peng, Shyh-An Chi
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Publication number: 20120124248Abstract: An information processor includes a central processing unit core and a tightly coupled smart memory unit, the central processing unit core having a direct memory access unit. The tightly coupled smart memory unit having a memory unit coupled to the central processing unit core and a control register, and status register coupled to the central processing unit core and a local processing unit that processes data stored in the memory unit.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Shyh-An CHI
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Publication number: 20120112352Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.Type: ApplicationFiled: November 10, 2010Publication date: May 10, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shyh-An CHI, Mark Shane PENG, Yun-Han LEE
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Publication number: 20110248759Abstract: A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.Type: ApplicationFiled: April 12, 2010Publication date: October 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shyh-An CHI, Shiue Tsong SHEN, Jyy Anne LEE, Yun-Han LEE
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Publication number: 20110095811Abstract: A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.Type: ApplicationFiled: June 4, 2010Publication date: April 28, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shyh-An CHI, Shiue Tsong SHEN, Jyy Anne LEE, Yun-Han LEE
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Publication number: 20100318816Abstract: A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.Type: ApplicationFiled: March 31, 2010Publication date: December 16, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shyh-An Chi, Jyy Anne Lee
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Publication number: 20100312934Abstract: A system and method for multi-protocol bus communications between integrated circuits is provided. An electronic system comprises an integrated circuit having an on-chip bus. The integrated circuit includes a master component and a first slave component, both coupled to the on-chip bus and communicate using a first on-chip bus protocol, a slave bus converter coupled to the on-chip bus, and a switch coupled to the slave bus converter and to the on-chip bus. The electronic system further comprising a second slave component coupled to the integrated circuit. The slave bus converter converts bus communications in the first on-chip bus protocol to a second on-chip bus protocol and the switch selectively couples the on-chip bus or the slave bus converter to the second slave component based on a bus select control signal.Type: ApplicationFiled: April 19, 2010Publication date: December 9, 2010Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., Global Unichip CorporationInventors: Shyh-An Chi, Jyy Anne Lee, Yung-Lo Li, Shih-Chi Wu
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Publication number: 20100264972Abstract: A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.Type: ApplicationFiled: April 12, 2010Publication date: October 21, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shyh-An CHI, Shiue Tsong SHEN, Jeff LEE, Frank Y. LEE
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Patent number: 7463096Abstract: This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.Type: GrantFiled: December 7, 2006Date of Patent: December 9, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-An Chi, Chih-Hung Chung
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Publication number: 20080136400Abstract: This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.Type: ApplicationFiled: December 7, 2006Publication date: June 12, 2008Inventors: Shyh-An Chi, Chih-Hung Chung
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Patent number: 7187163Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.Type: GrantFiled: January 19, 2005Date of Patent: March 6, 2007Assignee: Faraday Technology Corp.Inventors: Shyh-An Chi, Wang-Chin Chen
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Publication number: 20060197518Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.Type: ApplicationFiled: December 27, 2005Publication date: September 7, 2006Inventors: Shyh-An Chi, Wang-Jin Chen
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Publication number: 20060158178Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.Type: ApplicationFiled: January 19, 2005Publication date: July 20, 2006Inventors: Shyh-An Chi, Wang-Chin Chen
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Patent number: 6820191Abstract: An apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor is provided. The method includes adding the N bits in the N-bit decode information together to form an initial count value, and generating a plurality of register identification (ID) numbers equivalent in number to the initial count value. The register ID numbers correspond to the positions in the N-bit decode information that has a bit value ‘1’. According to the register ID number, a link is created between the plurality of registers corresponding to the register ID numbers and a memory unit so that the memory unit and the registers are free to exchange stored data.Type: GrantFiled: December 28, 2000Date of Patent: November 16, 2004Assignee: Faraday Technology Corp.Inventors: Calvin Guey, Shyh-An Chi, Yu-Min Wang