Abstract: An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by a triple-level polysilicon process which allows the bit lines to be formed by metal strips which have low resistance and which can cover the storage capacitors for alpha particle protection. Metal-to-silicon contacts are made through an intervening polysilicon segment which allows the underlying N+ silicon region to be much smaller than in prior cells. The polysilicon segment also prevents the occurrance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: Closely-spaced conductors can be used in a semiconductor integrated circuit such as an MOS read only memory or ROM formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, and output and ground lines are defined by elongated N+ regions. To allow the spacing between adjacent polysilicon address lines to be closer, alternate rows employ first or second level polysilicon which can even overlap if necessary. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide.

Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by a triple-level polysilicon process which allows the bit lines to be formed by metal strips which have low resistance and which can cover the storage capacitors for alpha particle protection. Metal-to-silicon contacts are made through an intervening polysilicon segment which allows the underlying N+ silicon region to be much smaller than in prior cells. The polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: Semiconductor read only memory (ROM) or electrically programmable memory (EPROM) devices are constructed using a metal-to-silicon contact arrangement which provides small cell size. An intervening polysilicon segment allows the silicon region underlying a metal contact area to be much smaller than in prior cells. The layout and cell structure provides a high density array. The use of the polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A plurality of dummy cells are connected to each column line half instead of a single dummy cell, and one of the dummy cells is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by spacing the dummy cells along each column line half, and addressing a dummy cell which is spaced about the same distance from the sense amplifier as the selected memory cell on the other side.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by placing the dummy cells at about the center of each column line half. The signals on the column line halves from the dummy cell and from the selected memory cell will reach the sense amplifier at about the same time, on average.