Abstract: A dynamic threshold voltage MOSFET to provide increase drain-to-source saturation current (I.sub.DSsat) and lower off current (I.sub.off) is described. The dynamic threshold voltage MOSFET has a first diffusion-well of a material of a first conductivity type formed at the surface of the substrate to form a bulk region. A source region and a drain region of a material of a second conductivity type are diffused into the diffusion-well. A first gate is then placed on a first oxide surface above the substrate between the source and drain regions. An accumulated base bipolar transistor is then placed on the semiconductor substrate. The base of the accumulated base bipolar transistor is connected to the gate, the emitter is connected to the diffusion-well. A resistor is connected between the emitter of the accumulated base bipolar transistor and a substrate biasing voltage source.

Abstract: A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time, the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

Abstract: This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.

Abstract: An accumulated-base bipolar junction transistor and an application of said transistor is described. A base region of an accumulated-base bipolar junction is formed by the implantation and then the diffusion of a first dopant material into the semiconductor substrate. A base contact region is a rectangular ring of a second dopant type that is implanted and annealed into the base region. The base contact region is to form a low resistance path from the base region to external circuitry. A collector region is formed by the implantation and annealing of third dopant into the base region in the form of a rectangular ring within the base contact region and a first distance from the base contact region. An emitter region is a rectangular form implanted and annealed of the third dopant within the collector region and a second distance from the collector region.

Abstract: A transient switching circuit is provided to generate a voltage signal with fast voltage switching phenomenon during the initial ESD transient. The voltage signal is applied to a current spike generator for generating a current spike which forward bias an n+/pwell diode for injecting minority carriers into a substrate on which ESD protection device is embodied. The injected minority carriers are used to trigger turn-on of the ESD protection device. These minority carriers flow toward the drain-substrate junction of the NMOS transistor such that the NMOS transistor is triggered at a trigger voltage lower than that provided by the prior arts. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract: A transient oscillating circuit is provided to generate a series of current pulses for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the series of current pulses injects minority carriers into the pwell of an NMOS transistor via an adjacent n+/pwell diode. These minority carriers flow toward the drain-substrate junction of the NMOS transistor such that the NMOS transistor is triggered at a trigger voltage lower than that provided by the prior arts. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract: A MOSFET device structure, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The MOSFET device structure features a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET device structure, formed from an ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector-base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.

Abstract: A MOS transistor current mirror having a low output voltage is described. A first and second MOST's have their drains and gates connected respectively to form MOS diodes. The drain of the first MOST is connected to a control constant current source and the source of first MOST is connected to the drain of the second MOST. The drain and gate of the first MOST are connected to the base of a bipolar junction transistor (BJT). The collector of the BJT is connected to a first power supply line and the emitter is connected to the gate of a third MOST. A resistor is connected between the emitter of the BJT and the a second power supply line. The gate and drain of the second MOST is connected to the gate of a fourth MOST. The sources of the second and fourth MOST's are connected to the second power supply line. The drain of the fourth MOST is connected to the source of the third MOST. The drain of the third MOST is connected to external circuitry.

Abstract: This invention describes an accumulated base bipolar junction transistor and an application of the accumulated base transistor as an input stage to an operational amplifier. The accumulated base transistor is formed during the processing of Complementary Metal Oxide Semiconductor Transistors. A metal gate is placed over the base region of the accumulated base transistor to form the base accumulator. The base accumulator will improve the gain of the bipolar junction transistor over a high frequency spectrum. The improved gain of the accumulated base transistor will cause an operational amplifier with accumulated-base bipolar transistors as an input stage to have improved performance characteristics over an operational amplifier using CMOS transistors as an input stage of the operational amplifier using the same integrated circuits processing techniques.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and short channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.

Abstract: A process for fabricating a MOSFET device, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The process features creating a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET, via ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector--base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.

Abstract: A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit is described. A semiconductor substrate is provided wherein NMOS and PMOS regions are separated by an isolation region. Gate electrodes are formed in the NMOS and PMOS regions. Lightly doped regions are implanted into the semiconductor substrate within the NMOS and PMOS regions. A spacer material layer is deposited over the gate electrodes in the NMOS and PMOS regions and etched away to leave spacers on the sidewalls of the gate electrodes. The NMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the PMOS region. The photoresist mask is removed. After the PMOS implantation, a portion of the spacers is etched away to leave narrower spacers on the sidewalls of the gate electrodes. The PMOS region is covered with a photoresist mask.