Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.

Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.

Abstract: A heat-pipe electric-power generating device capable of converting thermal energy to electrical energy is provided. The device includes a heat pipe and the heat pipe has a sealed internal space that can produce a steam-flow from an evaporating end to a condensing end according to a pressure difference caused by a temperature difference between the ends. A steam-flow electric-power generating device has at least a rotating portion disposed in the internal space for generating electric power when driven by a steam-flow. An electrode structure is used for leading the electric power out. The heat pipe is maintained in a sealed condition. In addition, several heat-pipe electric-power generating devices can be arranged into an array to form a heat electric-power generator or disposed inside an apparatus with a heat source for recycling the conventional waste thermal energy into useful electrical energy.

Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.

Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.

Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.

Abstract: An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.

Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.

Abstract: A wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract: a wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.

Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract: Lighting devices are provided. A lighting device includes a first substrate, a second substrate, a light source and a thermoelectric cooling chip set disposed between the first and second substrates. The first substrate includes a core, a first circuit layer, and a second circuit layer, wherein the first and second circuit layers are disposed on opposite sides of the core. The second substrate comprises a third circuit layer. The light source is disposed on the first substrate and electrically connected to the first circuit layer. The thermoelectric cooling chip set is electrically connected to the second and third circuit layers, to dissipate heat from the light source.

Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.

Abstract: Disclosed is a lighting device with flipped side-structure of LEDs, which allows emitted lights to travel in parallel with the mounting surface. Single or plural LED chips are mounted on a substrate with their side surfaces facing the substrate surface. The lighting device can be further combined with optical protrusions on the substrate to form a light module for reflecting and mixing lights emitted from the LED chips. It does not require a conventional wire bonding process. The packaging structure also resolves the heat dissipation problem of the LEDs. Electrostatic discharge protection circuits can be included in the light module if desired. The invention achieves good uniformity and high intensity of the combined lights with desired chromaticity.

Abstract: The present invention discloses a side structure of a bare LED and a backlight module thereof, wherein the backlight module is preferably a light source of a display device such as an LCD device. The backlight module includes a flat plate covered with a thermally conductive dielectric material, a plurality of the side structures of the bare LEDs placed on the flat plate and in contact with the thermally conductive dielectric material, and a plurality of reflection parts also placed on the flat plate, each side structure of each bare LED includes a bare LED and two electrically conductive materials coupled to two bonding pads of the side structure of the bare LED respectively, and positioned on the flat plate therefor.

Abstract: A structure of illuminating unit includes a point-like light-emitting device, having an optical axis. An initial-stage conoid-like reflective surface has a convergent opening end and a divergent opening end. The point-like light-emitting device is located at the convergent opening end and the optical axis is toward the divergent end for emitting light. The initial-stage conoid-like reflective surface and the optical axis include an initial-stage included angle. A final-stage conoid-like reflective surface has a convergent opening end and a divergent opening end. The convergent opening end of the final-stage conoid-like reflective surface is coupled with the divergent opening end of the initial-stage conoid-like reflective surface. The final-stage conoid-like reflective surface and the optical axis include a final-stage included angle. The initial-stage included angle is larger than the final-stage included angle.

Abstract: An LED lamp includes LED chips, an axle, and a lampshade. The LED chips are mounted on surface of the axle. The axle which is coupled to the lampshade includes heat pipes for transferring the heat generated by the LED chips to exterior of the lampshade and obtaining a better heat dissipation.