Patents by Inventor Shyue-Shyh Lin
Shyue-Shyh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120032268Abstract: A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Shyue-Shyh Lin, Li-Chun Tien
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Publication number: 20120015493Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.Type: ApplicationFiled: September 22, 2011Publication date: January 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pin Lin, Wen-Sheh Huang, Tian-Choy Gan, Chia-Lung Hung, Hsien-Chin Lin, Shyue-Shyh Lin
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Publication number: 20110291200Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: April 13, 2011Publication date: December 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ali KESHAVARZI, Ta-Pen GUO, Helen Shu-Hui CHANG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Shu-Min CHEN, Min CAO, Yung-Chin HOU
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Publication number: 20110291197Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.Type: ApplicationFiled: May 26, 2010Publication date: December 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng WU, Ali KESHAVARZI, Ka Hing FUNG, Ta-Pen GUO, Jiann-Tyng TZENG, Yen-Ming CHEN, Shyue-Shyh LIN, Shyh-Wei WANG, Sheng-Jier YANG, Hsiang-Jen TSENG, David B. SCOTT, Min CAO
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Publication number: 20110248348Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.Type: ApplicationFiled: April 8, 2010Publication date: October 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tian-Choy Gan, Hsien-Chin Lin, Chia-Pin Lin, Shyue-Shyh Lin, Li-Shiun Chen, Shin Hsien Liao
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Patent number: 8034677Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN, or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.Type: GrantFiled: February 25, 2010Date of Patent: October 11, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Pin Lin, Wen-Sheh Huang, Tian-Choy Gan, Chia-Lung Hung, Hsien-Chin Lin, Shyue-Shyh Lin
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Publication number: 20110227162Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.Type: ApplicationFiled: March 17, 2010Publication date: September 22, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pin LIN, Chien-Tai CHAN, Hsien-Chin LIN, Shyue-Shyh LIN
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Publication number: 20110207279Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.Type: ApplicationFiled: February 25, 2010Publication date: August 25, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pin LIN, Wen-Sheh HUANG, Tian-Choy GAN, Chia-Lung HUNG, Hsien-Chin LIN, Shyue-Shyh LIN
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Publication number: 20100317181Abstract: A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.Type: ApplicationFiled: March 30, 2010Publication date: December 16, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Wei Chung, Kuo-Feng Yu, Shyue-Shyh Lin
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Patent number: 7663237Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.Type: GrantFiled: December 27, 2005Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Ching Peng, Chloe Hsin-yi Chen, David Hsu-Wei Lwu, Shyue-Shyh Lin, Wei-Ming Chen
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Patent number: 7349234Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.Type: GrantFiled: April 29, 2005Date of Patent: March 25, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Ching Peng, Shyue-Shyh Lin, Wei-Ming Chen
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Publication number: 20070145519Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Yuan-Ching Peng, Chloe Chen, David Lwu, Shyue-Shyh Lin, Wei-Ming Chen
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Publication number: 20060120149Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.Type: ApplicationFiled: April 29, 2005Publication date: June 8, 2006Inventors: Yuan-Ching Peng, Shyue-Shyh Lin, Wei-Ming Chen
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Patent number: 6825133Abstract: A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer.Type: GrantFiled: January 22, 2003Date of Patent: November 30, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mo-Chiun Yu, Shyue-Shyh Lin
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Publication number: 20040142518Abstract: A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer.Type: ApplicationFiled: January 22, 2003Publication date: July 22, 2004Inventors: Mo-Chiun Yu, Shyue-Shyh Lin