Abstract: A three-dimensional semiconductor memory device may include a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure. The cell array structure may include a stack that includes interlayer insulating layers and conductive patterns alternately stacked with one another, a source structure on the stack, and a vertical structure that extends in the stack and is electrically connected to a bottom surface of the source structure. The vertical structure may include a channel layer that includes first portions respectively in vertical channel holes extending in the stack, and a second portion that extends in a region between the stack and the source structure and is electrically connected to the first portions.

Abstract: A vertical semiconductor device may include a substrate, a pattern structure on the substrate, and a channel structure in a channel hole passing through the pattern structure. The pattern structure may include insulation patterns and gate structures alternately stacked in a vertical direction perpendicular to an upper surface of the substrate. The channel structure may extend in the vertical direction. The channel structure may include a data storage structure on an inner surface of the channel hole, a channel contacting the data storage structure, a lower pattern on the channel positioned at a lower portion of the channel hole, and a filling insulation pattern on the channel and the lower pattern. The channel may have a cylindrical shape. The lower pattern may include an oxide including silicon and germanium.

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure by stacking interlayer insulating layers alternately with sacrificial layers on a plate layer, forming channel holes passing through the molded structure, forming channel layers doped with non-conductive impurities in the channel holes, forming a metal layer above the channel holes, forming metal silicide layers on upper ends of the channel layers using the metal layer, crystallizing the channel layers using the metal silicide layers by performing a heat treatment process at a temperature of 800 degrees or more, forming openings penetrating through the molded structure and extending in one direction, removing the sacrificial layers exposed through the openings, and forming gate electrodes, by filling regions from which the sacrificial layers have been removed, with a conductive material. After the crystallizing, the metal silicide layers are located lower than a lowermost gate electrode among the gate electrodes.

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked on a substrate, etching the stacked structure to form an opening exposing a part of the substrate through the stacked structure, forming a channel layer on a part of the substrate. The forming of the channel layer includes forming a first amorphous silicon layer at a first temperature on the part of the substrate by supplying a silicon source gas and an impurity source gas together and forming a second amorphous silicon layer at a second temperature on the first amorphous silicon layer by supplying the silicon source gas and not supplying the impurity source gas after the forming of the first amorphous silicon layer, and the second temperature is higher than the first temperature.

Abstract: A semiconductor memory device is disclosed. The device may include an electrode structure including electrodes, the electrodes stacked on a substrate, a source semiconductor layer between the substrate and the electrode structure, and a vertical channel structure penetrating the electrode structure. The vertical channel structure includes a vertical insulating pattern, a vertical semiconductor pattern spaced apart from the electrode structure with the vertical insulating pattern interposed between the vertical semiconductor pattern and the electrode structure; and a barrier pattern spaced apart from the electrode structure with the vertical semiconductor pattern interposed between the barrier pattern and the electrode structure. The vertical semiconductor pattern comprises a recess region, the source semiconductor layer extending in the recess region. The barrier pattern includes an insulating layer including carbon.