Abstract: The present invention relates to: a pyrene derivative compound having a specific structure; and a high efficiency organic light-emitting device employing the pyrene derivative compound in a light emitting layer and thus having excellent light-emitting characteristics. The organic light-emitting device according to the present invention can be configured as a high efficiency organic light-emitting device having excellent light-emitting characteristics by employing the pyrene derivative compound having the specific structure as a host in the light emitting layer, and thus can be usefully applied industrially in lighting devices, as well as various display devices such as flat, flexible, and wearable displays.

Abstract: An organic light-emitting device according to the present invention uses a pyrene derivative compound having a characteristic structure as a host in a light-emitting layer to realize a long-lifespan and high-efficiency organic light-emitting device having excellent light-emitting characteristics in terms of lifespan and luminescence efficiency. Accordingly, the organic light-emitting device can be usefully applied, in the industrial aspect, for various display devices such as flat panel, flexible, and wearable displays, as well as lighting devices.

Abstract: The present invention relates to a novel heterocyclic compound usable in an organic light-emitting device and to an organic light-emitting device comprising same, wherein [chemical formula A] is as described in the detailed description of the invention.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: Computer systems and related methods are provided for managing connections to storage devices. The computer system includes a connector and a register. The connector includes a plurality of pins configured to be removably connected to a first storage device and to a second storage device. A first pin of the connector carries a signal that indicates when the connector is connected to the first storage device, and a second pin carries a signal that indicates when the connector is connected to the second storage device. The register stores connection information that indicates whether the first storage device and/or the second storage device are connected to the connector.

Abstract: An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal, a second buffer for receiving data from the flash memory device in synchronization with the clock enable signal, a third buffer for receiving and outputting an output of the first buffer, and a latch circuit for latching an output of the second buffer in synchronization with output of the third buffer.

Abstract: A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error and a plurality of subsequent read data without outputting. The storing of the data is performed during the performing of the error correction operation.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: Computer systems and related methods are provided for managing connections to storage devices. The computer system includes a connector and a register. The connector includes a plurality of pins configured to be removably connected to a first storage device and to a second storage device. A first pin of the connector carries a signal that indicates when the connector is connected to the first storage device, and a second pin carries a signal that indicates when the connector is connected to the second storage device. The register stores connection information that indicates whether the first storage device and/or the second storage device are connected to the connector.

Abstract: An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal a second buffer for receiving data from the flash memory device in synchronization with the clock enable signal, a third buffer for receiving and outputting an output of the first buffer, and a latch circuit for latching an output of the second buffer in synchronization with output of the third buffer.

Abstract: A random number generator is provided that includes a plurality of bit generators for generating a first to last (e.g., 0'th to 30th) sum bits, a carry bit conversion section that receives a plurality of final output carries from a final bit generator of the plurality of bit generators and converts the received value to a prescribed-bit (e.g., 3-bit) signal, and a random number generation section adding the prescribed-bit signal outputted from the carry bit conversion section to the plurality of sum bits generated from the bit generation section to generate a random number. The random number generator is generated, for example, by adding a final output carry to a final sum generated from respective 31 bit generators to prevent wrap-around application of output carries of the final (e.g., 30th) a first bit generator to a 0'th bit generator.