Patents by Inventor Sia Choon Beng

Sia Choon Beng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11454799
    Abstract: Microscopes with objective assembly crash detection and methods of utilizing the same are disclosed herein. For example, a microscope comprises a microscope body, an objective assembly comprising an objective lens, an objective assembly mount configured to separably attach the objective assembly to the microscope body, and an orientation detection circuit configured to indicate when a relative orientation between the microscope body and the objective assembly differs from a predetermined relative orientation.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 27, 2022
    Assignee: FormFactor, Inc.
    Inventors: Gerald Lee Gisler, Sia Choon Beng, Anthony James Lord, Gavin Neil Fisher
  • Patent number: 11181550
    Abstract: Probe systems and methods including electric contact detection. The probe systems include a probe assembly and a chuck. The probe systems also include a translation structure configured to operatively translate the probe assembly and/or the chuck and an instrumentation package configured to detect contact between the probe system and a device under test (DUT) and to test operation of the DUT. The instrumentation package includes a continuity detection circuit, a test circuit, and a translation structure control circuit. The continuity detection circuit is configured to detect electrical continuity between a first probe electrical conductor and a second probe electrical conductor. The test circuit is configured to electrically test the DUT. The translation structure control circuit is configured to control the operation of the translation structure. The methods include monitoring continuity between a first probe and a second probe and controlling the operation of a probe system based upon the monitoring.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 23, 2021
    Assignee: FormFactor, lnc.
    Inventors: Sia Choon Beng, Kazuki Negishi
  • Patent number: 11016121
    Abstract: Methods of controlling the operation of probe stations and probe stations that perform the methods. The methods including generating a test routine by constructing a substrate map, receiving a test subset input from a user, and updating the substrate map to incorporate information regarding which devices under test (DUTS) of a plurality of DUTs are in a test subset of a plurality of DUTs. The methods also include receiving a pre-test subset input from the user, wherein the pre-test subset is a subset of the test subset, and updating the substrate map to incorporate information which DUTs of the test subset are in the pre-test subset. The methods further include executing the test routine by moving a probe assembly to each DUT in the test subset, selectively performing a pre-test routine on each DUT that is in the pre-test subset, and electrically testing each DUT in the test subset.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 25, 2021
    Assignee: FormFactor, Inc.
    Inventors: Sia Choon Beng, David Randle Hess, Chunyi Yin Leong
  • Publication number: 20200241278
    Abstract: Microscopes with objective assembly crash detection and methods of utilizing the same are disclosed herein. For example, a microscope comprises a microscope body, an objective assembly comprising an objective lens, an objective assembly mount configured to separably attach the objective assembly to the microscope body, and an orientation detection circuit configured to indicate when a relative orientation between the microscope body and the objective assembly differs from a predetermined relative orientation.
    Type: Application
    Filed: January 24, 2020
    Publication date: July 30, 2020
    Inventors: Gerald Lee Gisler, Sia Choon Beng, Anthony James Lord, Gavin Neil Fisher
  • Publication number: 20190369141
    Abstract: Probe stations for testing a plurality of devices under test and associated methods are disclosed herein. The methods include generating a test routine and executing the test routine. The probe stations include probe stations that perform the methods.
    Type: Application
    Filed: May 23, 2019
    Publication date: December 5, 2019
    Inventors: Sia Choon Beng, David Randle Hess, Chunyi Yin Leong
  • Publication number: 20190277885
    Abstract: Probe systems and methods including electric contact detection. The probe systems include a probe assembly and a chuck. The probe systems also include a translation structure configured to operatively translate the probe assembly and/or the chuck and an instrumentation package configured to detect contact between the probe system and a device under test (DUT) and to test operation of the DUT. The instrumentation package includes a continuity detection circuit, a test circuit, and a translation structure control circuit. The continuity detection circuit is configured to detect electrical continuity between a first probe electrical conductor and a second probe electrical conductor. The test circuit is configured to electrically test the DUT. The translation structure control circuit is configured to control the operation of the translation structure. The methods include monitoring continuity between a first probe and a second probe and controlling the operation of a probe system based upon the monitoring.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Sia Choon Beng, Kazuki Negishi
  • Patent number: 10330703
    Abstract: Probe systems and methods including electric contact detection. The probe systems include a probe assembly and a chuck. The probe systems also include a translation structure configured to operatively translate the probe assembly and/or the chuck and an instrumentation package configured to detect contact between the probe system and a device under test (DUT) and to test operation of the DUT. The instrumentation package includes a continuity detection circuit, a test circuit, and a translation structure control circuit. The continuity detection circuit is configured to detect electrical continuity between a first probe electrical conductor and a second probe electrical conductor. The test circuit is configured to electrically test the DUT. The translation structure control circuit is configured to control the operation of the translation structure. The methods include monitoring continuity between a first probe and a second probe and controlling the operation of a probe system based upon the monitoring.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 25, 2019
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Sia Choon Beng, Kazuki Negishi
  • Publication number: 20180284155
    Abstract: Probe systems and methods including electric contact detection. The probe systems include a probe assembly and a chuck. The probe systems also include a translation structure configured to operatively translate the probe assembly and/or the chuck and an instrumentation package configured to detect contact between the probe system and a device under test (DUT) and to test operation of the DUT. The instrumentation package includes a continuity detection circuit, a test circuit, and a translation structure control circuit. The continuity detection circuit is configured to detect electrical continuity between a first probe electrical conductor and a second probe electrical conductor. The test circuit is configured to electrically test the DUT. The translation structure control circuit is configured to control the operation of the translation structure. The methods include monitoring continuity between a first probe and a second probe and controlling the operation of a probe system based upon the monitoring.
    Type: Application
    Filed: March 23, 2018
    Publication date: October 4, 2018
    Inventors: Sia Choon Beng, Kazuki Negishi
  • Patent number: 6777774
    Abstract: A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: August 17, 2004
    Assignee: Chartered Semiconductor Manufacturing Limited
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu, Lap Chan, Chew Kok-Wai
  • Patent number: 6714112
    Abstract: A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: March 30, 2004
    Assignee: Chartered Semiconductor Manufacturing Limited
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu
  • Publication number: 20030210121
    Abstract: A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.
    Type: Application
    Filed: May 10, 2002
    Publication date: November 13, 2003
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu
  • Publication number: 20030197243
    Abstract: A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.
    Type: Application
    Filed: April 17, 2002
    Publication date: October 23, 2003
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu, Lap Chan, Chew Kok-Wai
  • Patent number: 6608362
    Abstract: A method of fabricating high quality passive components having reduced capacitive and magnetic effects by using a Schottky diode underlying the passive components in the manufacture of integrated circuits is described. A Schottky diode is formed completely covering an active area where passive devices are to be formed. The Schottky diode is covered with a dielectric layer. Passive components are formed overlying the dielectric layer wherein the Schottky diode reduces substrate noise resulting in high quality of the passive components.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: August 19, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shao Kai, Sanford Chu, Chit Hwei Ng, Jia Zhen Zheng, Sia Choon Beng, Chew Kok Wai
  • Patent number: 6486017
    Abstract: A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric material overlying the surface of the substrate, the islands of first dielectric material align with coils of a thereover to be created spiral inductor. The openings created in the layer of dielectric by the patterning and etching of the first layer of dielectric are filled by selective deposition of epitaxial silicon therein. Second and third layers of dielectric are successively deposited over the surface of the first layer of dielectric. A spiral horizontal inductor is then created over the surface of the third layer of dielectric.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 26, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Purakh Raj Verma, Sanford Chu, Johnny Chew, Sia Choon Beng