Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract: Inventive aspects include one or more local servers each including a local universal access logic section, one or more remote servers each including a remote universal access logic section, and a coherency node to provide coherent access to first data that is stored on the one or more local servers to the one or more remote servers, and to provide coherent access to second data that is stored on the one or more remote servers to the one or more local servers. Embodiments of the inventive concept herein can use hardware and/or software mechanism to unify direct and remote attached devices via command, data, status, and completion memory queues. Applications and operating systems can be presented with a uniform access interface for sharing data and resources across multiple disparately situated servers and nodes.

Abstract: A memory module includes a solid-state drive (SSD) and a memory controller. The memory controller receives information from a host memory controller via a synchronous memory channel and determines to initiate background tasks of the SSD based on memory commands and a state of the memory module. According to one embodiment, the synchronous memory channel is a DRAM memory channel, and the SSD includes a flash memory. The background tasks of the SSD such as garbage collection, wear leveling, and erase block preparation are initiated during an idle state of the memory module.

Abstract: A storage device for deduplicating data includes a memory that stores machine instructions and a controller coupled to the memory to execute the machine instructions in order to compare a data pattern associated with a write request to stored data. If the data pattern matches the stored data, the controller further executes the machine instructions to increment a counter associated with the data pattern and map a source storage address corresponding to the data pattern to a physical storage address associated with the storage device.

Abstract: An electronic system includes: a management server providing a management mechanism with an address structure having a unified address space; a communication block, coupled to the management server, configured to implement a communication transaction based on the management mechanism with the address structure having the unified address space; and a server, coupled to the communication block, providing the communication transaction with a storage device based on the management mechanism with the address structure having the unified address space.

Abstract: Inventive aspects include one or more local servers each including a local universal access logic section, one or more remote servers each including a remote universal access logic section, and a coherency node to provide coherent access to first data that is stored on the one or more local servers to the one or more remote servers, and to provide coherent access to second data that is stored on the one or more remote servers to the one or more local servers. Embodiments of the inventive concept herein can use hardware and/or software mechanism to unify direct and remote attached devices via command, data, status, and completion memory queues. Applications and operating systems can be presented with a uniform access interface for sharing data and resources across multiple disparately situated servers and nodes.

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract: Systems and methods for extending the memory resources of a user device to storage resources and/or network resources associated with the user device. The cache and system memory of the user device may be utilized as a cache memory and the storage resources and/or network resources of the user device may be utilized as a storage memory.

Abstract: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device includes a plurality of memory cells. At least one of the memory cells includes a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element. Each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

Abstract: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element.

Abstract: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element.

Abstract: The present invention generally comprises an on-chip interconnection apparatus. The apparatus, in one embodiment, includes programmable routing elements and communication segments coupled between the routing elements and multiple system units. In one embodiment, a first traffic stream is transferred between two of the system units through at least one of the programmable routing elements and at least one of the segments. At the same time, a second traffic stream is transferred between two of the system units through at least one of the programmable routing elements and at least one of the segments. In a preferred embodiment, the first traffic stream and the second traffic stream comprise distinct traffic classes.

Abstract: An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP operations as loop iterations such that there is maximal reuse of data between multiple consecutive iterations. Independent set up and preparation of data before it is required through suitable mechanisms such as data pre-fetching may be used. This technique may be useful and important for devices that require cost-effective, high-performance, power consumption efficient VLSI IC.

Abstract: An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP operations as loop iterations such that there is maximal reuse of data between multiple consecutive iterations. Independent set up and preparation of data before it is required through suitable mechanisms such as data pre-fetching may be used. This technique may be useful and important for devices that require cost-effective, high-performance, power consumption efficient VLSI IC.

Abstract: An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP operations as loop iterations such that there is maximal reuse of data between multiple consecutive iterations. Independent set up and preparation of data before it is required through suitable mechanisms such as data pre-fetching may be used. This technique may be useful and important for devices that require cost-effective, high-performance, power consumption efficient VLSI IC.

Abstract: The present invention generally comprises an on-chip interconnection apparatus. The apparatus, in one embodiment, includes programmable routing elements and communication segments coupled between the routing elements and multiple system units. In one embodiment, a first traffic stream is transferred between two of the system units through at least one of the programmable routing elements and at least one of the segments. At the same time, a second traffic stream is transferred between two of the system units through at least one of the programmable routing elements and at least one of the segments. In a preferred embodiment, the first traffic stream and the second traffic stream comprise distinct traffic classes.

Abstract: A system includes a docking base unit having a first processor and a portable computing device that is dockable to the docking base unit that includes a second processor. A module identifies the number of processors in the system once the portable computing device is docked to the docking base unit and configures the system as a multiprocessor system if more than one processor is identified.