Patents by Inventor Sibina Sukman
Sibina Sukman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7372072Abstract: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements.Type: GrantFiled: December 15, 2005Date of Patent: May 13, 2008Assignee: Infineon Technologies AGInventors: Ramona Winter, Susanne Lachenmann, Valentin Rosskopf, Sibina Sukman-Praehofer
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Patent number: 7205567Abstract: A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.Type: GrantFiled: January 20, 2006Date of Patent: April 17, 2007Assignee: Infineon Technologies AGInventors: Andreas Felber, Susanne Lachenmann, Valentin Rosskopf, Sibina Sukman-Praehofer
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Patent number: 7126154Abstract: A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.Type: GrantFiled: September 3, 2004Date of Patent: October 24, 2006Assignee: Infineon Technologies AGInventors: Valentine Rosskopf, Susanne Lachenmann, Sibina Sukman-Prähofer, Andreas Felber
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Publication number: 20060175647Abstract: A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.Type: ApplicationFiled: January 20, 2006Publication date: August 10, 2006Inventors: Andreas Felber, Susanne Lachenmann, Valentin Rosskopf, Sibina Sukman-Praehofer
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Publication number: 20060157700Abstract: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements.Type: ApplicationFiled: December 15, 2005Publication date: July 20, 2006Inventors: Ramona Winter, Susanne Lachenmann, Valentin Rosskopf, Sibina Sukman-Praehofer
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Publication number: 20060157702Abstract: A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the fill patterns in the kerf and the device patterns in the chip areas are essentially similarly constructed.Type: ApplicationFiled: January 19, 2006Publication date: July 20, 2006Applicant: INFINEON TECHNOLOGIES AGInventors: Sibina Sukman-Prahofer, Susanne Lachenmann, Valentin Rosskopf, Ramona Winter
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Publication number: 20060138411Abstract: The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) are connected by means of contact elements (4) arranged above them, to a third interconnect (3) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect (2). If there is a parasitic contact structure (5) formed between the contact elements (4), which has arisen during the lithographic exposure for producing the contact elements (4) on account of constructively interfering diffraction maxima, then this shorts the second interconnect (2) to the third interconnect (3).Type: ApplicationFiled: December 2, 2005Publication date: June 29, 2006Inventors: Susanne Lachenmann, Valentin Rosskopf, Sibina Sukman-Praehofer, Ramona Winter
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Patent number: 6917208Abstract: A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are interconnected to form a ring structure. Two measurement pads are in each case provided at the nodes between two resistors. The measurement pads can be used for feeding in current and for measuring voltage according to the known four-point measurement method. The effect of the ring structure is that fewer measurement pads are required, in contrast to the customary series circuit of resistors. By way of example, in the case of a ring structure with four resistors, two measurement pads are advantageously saved. The consequently reduced chip area required for the ring structure is advantageous particularly in the case of test circuits, which can be arranged for example in the narrow sawing frame between two chips.Type: GrantFiled: April 4, 2003Date of Patent: July 12, 2005Assignee: Infineon Technologies AGInventors: Jürgen Lindolf, Sibina Sukman
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Publication number: 20050051765Abstract: A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.Type: ApplicationFiled: September 3, 2004Publication date: March 10, 2005Applicant: INFINEON TECHNOLOGIES AGInventors: Valentin Rosskopf, Susanne Lachenmann, Sibina Sukman-Prahofer, Andreas Felber
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Patent number: 6856562Abstract: A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.Type: GrantFiled: September 11, 2003Date of Patent: February 15, 2005Assignee: Infineon Technologies AGInventors: Susanne Lachenmann, Valentin Rosskopf, Andreas Felber, Sibina Sukman
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Publication number: 20040057292Abstract: A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.Type: ApplicationFiled: September 11, 2003Publication date: March 25, 2004Inventors: Susanne Lachenmann, Valentin Rosskopf, Andreas Felber, Sibina Sukman
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Publication number: 20030189436Abstract: A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are interconnected to form a ring structure. Two measurement pads are in each case provided at the nodes between two resistors. The measurement pads can be used for feeding in current and for measuring voltage according to the known four-point measurement method. The effect of the ring structure is that fewer measurement pads are required, in contrast to the customary series circuit of resistors. By way of example, in the case of a ring structure with four resistors, two measurement pads are advantageously saved. The consequently reduced chip area required for the ring structure is advantageous particularly in the case of test circuits, which can be arranged for example in the narrow sawing frame between two chips.Type: ApplicationFiled: April 4, 2003Publication date: October 9, 2003Inventors: Jurgen Lindolf, Sibina Sukman