Patents by Inventor Siddarth Kumar

Siddarth Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240169564
    Abstract: A computer-implemented method for tracking surgical textiles includes receiving a first image comprising a first textile-depicting image region, receiving a second image comprising a second textile-depicting image region, measuring a likelihood that the first and second image regions depict at least a portion of the same textile, and incrementing an index counter if the measure of likelihood does not meet a predetermined threshold. The measure of likelihood may be based on at least one classification feature at least partially based on aspects or other features of the first and second images.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 23, 2024
    Applicant: Gauss Surgical Inc.
    Inventors: Mayank Kumar, Kevin J. Miller, Siddarth Satish
  • Patent number: 11922646
    Abstract: A computer-implemented method for tracking surgical textiles includes receiving a first image comprising a first textile-depicting image region, receiving a second image comprising a second textile-depicting image region, measuring a likelihood that the first and second image regions depict at least a portion of the same textile, and incrementing an index counter if the measure of likelihood does not meet a predetermined threshold. The measure of likelihood may be based on at least one classification feature at least partially based on aspects or other features of the first and second images.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: March 5, 2024
    Assignee: Gauss Surgical Inc.
    Inventors: Mayank Kumar, Kevin J. Miller, Siddarth Satish
  • Patent number: 11276625
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Shubhada H. Sahasrabudhe, Sandeep B. Sane, Shalabh Tandon
  • Publication number: 20210280495
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Siddarth Kumar, Shubhada H. Sahasrabudhe, Sandeep B. Sane, Shalabh Tandon
  • Patent number: 10748844
    Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Shawna M. Liff
  • Publication number: 20190206782
    Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Siddarth KUMAR, Shawna M. LIFF
  • Patent number: 9953934
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Sandeep B Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Patent number: 9930793
    Abstract: Generally discussed herein are systems and apparatuses that can include a flexible substrate with a hermetic seal formed thereon. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a hermetic seal on a flexible substrate can include (1) forming an interconnect on a flexible substrate, (2) situating a device on the substrate near the interconnect, or (3) selectively depositing a first hermetic material on the device or interconnect so as to hermetically seal the device within the combination of the interconnect and first hermetic material.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Siddarth Kumar
  • Patent number: 9735089
    Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Hemanth K. Dhavaleswarapu
  • Publication number: 20170178987
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Siddarth Kumar, Sandeep B. Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Patent number: 9659908
    Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Shubhada H. Sahasrabudhe, Sandeep B Sane, Siddarth Kumar, Shalabh Tandon
  • Publication number: 20170133350
    Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Shubhada H. Sahasrabudhe, Sandeep B. Sane, Siddarth Kumar, Shalabh Tandon
  • Publication number: 20170092564
    Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventors: Siddarth Kumar, Hemanth K. Dhavaleswarapu
  • Publication number: 20150282341
    Abstract: Generally discussed herein are systems and apparatuses that can include a flexible substrate with a hermetic seal formed thereon. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a hermetic seal on a flexible substrate can include (1) forming an interconnect on a flexible substrate, (2) situating a device on the substrate near the interconnect, or (3) selectively depositing a first hermetic material on the device or interconnect so as to hermetically seal the device within the combination of the interconnect and first hermetic material.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Chuan Hu, Siddarth Kumar
  • Patent number: 8454023
    Abstract: The present application thus provides a retractable seal system for use between a high pressure side and a low pressure side of a turbine engine. The retractable seal system may include a seal positioned in a slot of a stationary component, a pressure balance pocket positioned about the seal, and a conduit in communication with the pressure balance pocket and the high pressure side.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 4, 2013
    Assignee: General Electric Company
    Inventors: Omprakash Samudrala, Siddarth Kumar, Gregory A. Crum, Karimulla Shaik Sha
  • Publication number: 20120286476
    Abstract: The present application thus provides a retractable seal system for use between a high pressure side and a low pressure side of a turbine engine. The retractable seal system may include a seal positioned in a slot of a stationary component, a pressure balance pocket positioned about the seal, and a conduit in communication with the pressure balance pocket and the high pressure side.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 15, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Omprakash Samudrala, Siddarth Kumar, Gregory Crum, Karimulla Shaik Sha