Abstract: A security trimming system disclosed herein uses intelligent caching of the security trimming information received from a security datastore. The security trimming system uses an access cache to store the security trimming information received from the access datastore together with other parameters associated with such security trimming information. Subsequently, in responding to a request for the security trimming information, the security trimming system uses the cached value of the security trimming information together with the other associated parameters to determine a response to the request from the content providers. In one implementation, if the other parameters associated with a particular security trimming information imply that the security trimming information in the cache is still valid, the cached security trimming information is used in the request response. Otherwise, a new request is sent to the security datastore for an updated value of the security trimming information.

Abstract: A security trimming system disclosed herein uses intelligent caching of the security trimming information received from a security datastore. The security trimming system uses an access cache to store the security trimming information received from the access datastore together with other parameters associated with such security trimming information. Subsequently, in responding to a request for the security trimming information, the security trimming system uses the cached value of the security trimming information together with the other associated parameters to determine a response to the request from the content providers. In one implementation, if the other parameters associated with a particular security trimming information imply that the security trimming information in the cache is still valid, the cached security trimming information is used in the request response. Otherwise, a new request is sent to the security datastore for an updated value of the security trimming information.

Abstract: Balancing resource allocations based on priority may be provided. First, a plurality of repositories may be divided into at least two categories. Next, a first portion of computing resources may be dedicated to a first one of the at least two categories. Then a second portion of the computing resources may be dedicated to a second one of the at least two categories. A crawl may then be performed on the plurality of repositories with the computing resources.

Abstract: A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.

Abstract: An array substitution scheme is used to substitute a spare chip for a faulty chip when a UE condition results from an alignment of two errors in bit positions accessed through the same decoder while the bit permutation apparatus is used to misalign fault bits when they occur in bit positions accessed through different decoders.