Abstract: The present invention provides an integrated circuit and method of manufacture therefore. The integrated circuit, in one embodiment, includes heat conducting elements located proximate a plurality of heat generating components located over a substrate. The integrated circuit may further include a heat radiating element comprising one or more fins in thermal communication and physical contact with the heat conducting elements, the heat radiating element configured to dissipate heat generated by the heat generating components away from the integrated circuit.

Abstract: The present invention provides an integrated circuit and method of manufacture therefore. The integrated circuit, in one embodiment, includes heat conducting elements located proximate a plurality of heat generating components located over a substrate. The integrated circuit may further include a heat radiating element comprising one or more fins in thermal communication and physical contact with the heat conducting elements, the heat radiating element configured to dissipate heat generated by the heat generating components away from the integrated circuit.

Abstract: A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 ?m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

Abstract: A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

Abstract: A metal oxide semiconductor (MOS) capacitor formed according to a process in which Fermi level enhanced oxidation is suppressed by the introduction of nitrogen impurities into an N-doped impurity region is formed to utilize the N-doped impurity region as a lower electrode and includes a capacitor dielectric having a reduced thickness with respect to other portions of the thermal oxide film formed over N-doped impurity regions. The capacitor is highly linear and includes a high capacitance density. The process used to form the capacitor includes thermally oxidizing a substrate such that an oxide film is formed to include multiple thicknesses including an enhanced oxide growth rate producing an oxide film of increased thickness in N-doped impurity regions and a section within nitrogen-doped impurity portions of the N-doped impurity region in which the enhanced oxidation growth is suppressed and the film formed in this region includes a desirably reduced thickness.

Abstract: A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.

Abstract: A metal oxide semiconductor (MOS) capacitor formed according to a process in which Fermi level enhanced oxidation is suppressed by the introduction of nitrogen impurities into an N-doped impurity region is formed to utilize the N-doped impurity region as a lower electrode and includes a capacitor dielectric having a reduced thickness with respect to other portions of the thermal oxide film formed over N-doped impurity regions. The capacitor is highly linear and includes a high capacitance density. The process used to form the capacitor includes thermally oxidizing a substrate such that an oxide film is formed to include multiple thicknesses including an enhanced oxide growth rate producing an oxide film of increased thickness in N-doped impurity regions and a section within nitrogen-doped impurity portions of the N-doped impurity region in which the enhanced oxidation growth is suppressed and the film formed in this region includes a desirably reduced thickness.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: The present invention provides a method of forming a metal oxide metal (MOM)capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.

Abstract: The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor.

Abstract: A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.

Abstract: The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor.

Abstract: A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of metal conductive films to the device. The process sequence includes a three-step passivation, de-passivation, re-passivation sequence and utilizes a barrier film to encapsulate deuterium molecules in the vicinity of a gate oxide, during the de-passivation operation.