Abstract: A method and system for configuring ultraviolet (UV)-based nanoimprint lithography (NIL) for roll-to-roll (R2R) processing, which combines the benefits of inexpensive R2R processing with the precise nanoscale patterning afforded by NIL. Furthermore, an R2R fabrication process is used to create nanoscale copper (Cu) metal mesh electrodes on flexible polycarbonate substrates and rigid quartz substrates employing jet-and-flash nanoimprint lithography (J-FIL), linear ion source etching (LIS) and selective electroless Cu metallization (ECu) using a palladium (Pd) seed layer.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: Various embodiments of the present technology generally relate to semiconductor device architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to large area metrology and process control for anisotropic chemical etching. Catalyst influenced chemical etching (CICE) can be used to create high aspect ratio semiconductor structures with dimensions in the nanometer to millimeter scale with anisotropic and smooth sidewalls. However, all aspects of the CICE process must be compatible with the equipment used in semiconductor fabrication facilities today, and they must be scalable to enable wafer scale processing with high yield and reliability. This invention relates to metrology and control of etch and CMOS compatible methods of patterning the catalyst and removing it without damaging the etched structures.

Abstract: Various embodiments of the present technology generally relate to substrate planarization. More specifically, some embodiments of the present technology relate a versatile systems and methods for precision surface topography optimization known as planarization on nominally planar substrates. In some embodiments, a method for planarization of a patterned substrate using inkjets can determine the global and nanoscale topography and pattern information of the patterned substrate. Based upon the global and nanoscale topography and pattern information, a drop pattern can be determined and then dispensed on the patterned substrate. A gap between the patterned substrate and a superstrate causing the dispensed drops can be closed to form a substantially contiguous film. The substantially contiguous film can be cured and the superstrate can be separated from the patterned substrate with substantially contiguous film on the patterned substrate.

Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.

Abstract: Control of lateral strain and lateral strain ratio (dt/db) between template and substrate through the selection of template and/or substrate thicknesses (Tt and/or Tb), control of template and/or substrate back pressure (Pt and/or Pb), and/or selection of material stiffness are described.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: A method and alignment system for minimizing errors in the deposition of films of tailored thickness. A first position on a stage is identified for optimal placement of a downward looking microscope (DLM) and an upward looking microscope (ULM) when alignment marks on the DLM and ULM are aligned, where the DLM is attached to a bridge and the ULM is attached to the stage. A second position on the stage is identified when the ULM on the stage is aligned with the alignment marks on a metrology tool. A surface of a chucked substrate affixed to the stage is then measured. A map between a substrate coordinate system and a metrology coordinate system may then be obtained using the measured surface of the chucked substrate with the first and second positions.

Abstract: A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently. The portable system is used for the design and assembly of a prototype tool with all the functionalities or a subset of functionalities present in a master tool used in a small tech factory.

Abstract: Systems and methods for partial field imprinting are provided such that imprint templates are asymmetrically modulated to allow initial contact with a partial field on a substrate at a location spaced apart from the template center.

Abstract: A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently.

Abstract: Control of lateral strain and lateral strain ratio (dt/db) between template and substrate through the selection of template and/or substrate thicknesses (Tt and/or Tb), control of template and/or substrate back pressure (Pt and/or Pb), and/or selection of material stiffness are described.

Abstract: Techniques for delivering sub-5 nm overlay control over multiple fields. One such technique reduces overlay from the wafer side using wafer-thermal actuators. In another technique, the topology of the template is optimized so that the inter-field mechanical coupling between fields in the multi-field template is reduced thereby allowing overlay to be simultaneously reduced in multiple fields in the template. A further technique combines the wafer-thermal and template actuation techniques to achieve significantly improved single and multi-field overlay performance.

Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.

Abstract: A method for depositing thin films using a nominally curved substrate. Drops of a pre-cursor liquid organic material are dispensed at a plurality of locations on a nominally curved substrate by one or more inkjets. A superstrate is brought down on the dispensed drops to close the gap between the superstrate and the substrate thereby allowing the drops to form a contiguous film captured between the substrate and the superstrate. A non-equilibrium transient state of the superstrate, the contiguous film and the substrate is enabled to occur after a duration of time. The contiguous film is then cured to solidify it into a solid. The solid is separated from the superstrate thereby leaving a polymer film on the substrate. In this manner, such a technique for film deposition has the film thickness range, resolution and variation required to be applicable for a broad spectrum of applications.

Abstract: A nanoimprint lithography template including, inter alia, a body having first and second opposed sides with a first surface disposed on the first side, the second side having a recess disposed therein, the body having first and second regions with the second region surrounding the first region and the recess in superimposition with the first region, with a portion of the first surface in superimposition with the first region being spaced-apart from the second side a first distance and a portion of the first surface in superimposition with the second region being spaced-apart from the second side a second distance, with the second distance being greater than the first distance; and a mold disposed on the first side of the body in superimposition a portion of the first region.