Abstract: Individual coils as well as two or more coils arranged one over the other or one coil in combination with a sensor, which can be integrated into planar semiconductor technology are described. A coil comprises a turn and two supply lines for supplying current to the coil. The turn and the supply lines are formed from a metal layer. One of the two supply lines is connected to a first end of the turn and the other of the two supply lines is connected to a second end of the turn.

Abstract: A method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).

Abstract: The invention relates to a method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).

Abstract: A method and device for determining the thicknesses of semiconductor membranes uses electrical measurements. Energy is coupled into the membrane in a defined manner and the membrane thickness is determined from the distribution or diffusion of the energy. A change of state of the membrane is detected by measuring electroconductivity of measuring resistances at least one of which is on the membrane. The electroconductivity varies according to the temperature and the mechanical strain of the membrane, which both depend on the thickness of the membrane.

Abstract: A method for the electrical measurement of the thickness of a semiconductor layer ( 10, 11, 12) is disclosed. Active layers on SOI wafers, EPI layers with inverse conductivity tape and membrane thickness can be measured by use of a test structure which can routinely be measured during a production process. The embodiment of the test structure (A1 to F1) is preferably annular, such that a high degree of symmetry is achieved on propagation of the measuring current and such that no interactions occur with surrounding structures. The diameter of the arrangement can be matched to the corresponding thickness range of the semiconductor layer to be measured using conventional U-I parameter test systems, conventionally applied in semiconductor production. The determination of the layer thickness is achieved by means of two sequential quadrupole measurements at six contact points.