Patents by Inventor Siegfried K. H. Sutter

Siegfried K. H. Sutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selectively isolating processor elements into subsets of processor elements
    Patent number: 8532288
    Abstract: A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks that are smaller than the maximum capability of the engine in terms of bits multiplied at one time. The serially connected hardware is thus partitioned on the fly to process a variety of cryptographic key sizes while still maintaining all of the hardware in an active processing state.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Camil Fayad, John K. Li, Siegfried K. H. Sutter, Phil C. Yeh
  • Forward shifting of processor element processing for load balancing
    Patent number: 7890559
    Abstract: A data processing system, which is particularly useful for carrying out modular multiplication, especially for cryptographic purposes, comprises a plurality of independent, serially connected processing elements which are provided with data in a cyclical fashion via a control mechanism that is capable of transferring data from a set of registers to earlier ones in the series of the serially connected processing elements, at the end of a predetermined number of cycles.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Camil Fayad, John K. Li, Siegfried K. H. Sutter, Tamas Visegrady
  • Load balancing for a system of cryptographic processors
    Patent number: 7870395
    Abstract: In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Dewkett, Camil Fayad, John K. Li, Siegfried K. H. Sutter, Phil C. Yeh
  • FORWARD SHIFTING OF PROCESSOR ELEMENT PROCESSING FOR LOAD BALANCING
    Publication number: 20080152127
    Abstract: A data processing system, which is particularly useful for carrying out modular multiplication, especially for cryptographic purposes, comprises a plurality of independent, serially connected processing elements which are provided with data in a cyclical fashion via a control mechanism that is capable of transferring data from a set of registers to earlier ones in the series of the serially connected processing elements, at the end of a predetermined number of cycles.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Camil Fayad, John K. Li, Siegfried K.H. Sutter, Tamas Visegrady
  • RUNTIME CONFIGURABILITY FOR CRT & NON CRT MODE
    Publication number: 20080130874
    Abstract: A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks that are smaller than the maximum capability of the engine in terms of bits multiplied at one time. The serially connected hardware is thus partitioned on the fly to process a variety of cryptographic key sizes while still maintaining all of the hardware in an active processing state.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Camil Fayad, John K. Li, Siegfried K.H. Sutter, Phil C. Yeh
  • LOAD BALANCING FOR A SYSTEM OF CRYPTOGRAPHIC PROCESSORS
    Publication number: 20080098233
    Abstract: In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.
    Type: Application
    Filed: October 20, 2006
    Publication date: April 24, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Dewkett, Camil Fayad, John K. Li, Siegfried K.H. Sutter, Phil C. Yeh