Patents by Inventor Siegfried Maurer
Siegfried Maurer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8642431Abstract: A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.Type: GrantFiled: April 2, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Patent number: 8476152Abstract: A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.Type: GrantFiled: March 31, 2012Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Patent number: 8343863Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.Type: GrantFiled: January 25, 2012Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Publication number: 20120190177Abstract: A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.Type: ApplicationFiled: March 31, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Publication number: 20120190161Abstract: A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.Type: ApplicationFiled: April 2, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Publication number: 20120135587Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.Type: ApplicationFiled: January 25, 2012Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Patent number: 8178430Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.Type: GrantFiled: April 8, 2009Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Publication number: 20100261319Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.Type: ApplicationFiled: April 8, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
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Publication number: 20050170570Abstract: A SIMOX (separation by implanted oxygen) process is provided that forms a silicon-on-insulator (SOI) substrate having a buried oxide with improved electrical properties. The process implements at least one of the following processing steps into SIMOX: (I) lowering of the oxygen ion dose in the base oxygen ion implant step; (II) off-setting the implant energy of the room temperature (RT) implant step to a value that is about 5 to about 20% lower than the base ion implant step; and (III) creating a soak cycle, i.e., pre-annealing step, prior to the internal oxidation anneal which allows dissolution of Si and SiOx precipitates in the oxygen implanted region. The temperature and time of the soak cycle as well as the base implant dose are critical in determining the final BOX quality.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel DeSouza, Keith Fogel, Harold Hovel, Junedong Lee, Siegfried Maurer, Devendra Sadana, Dominic Schepis
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Publication number: 20050067055Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kwang Choe, Keith Fogel, Siegfried Maurer, Ryan Mitchell, Devendra Sadana
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Publication number: 20050003626Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.Type: ApplicationFiled: July 22, 2004Publication date: January 6, 2005Inventors: Stephen Fox, Neena Garg, Kenneth Giewont, Junedong Lee, Siegfried Maurer, Dan Moy, Maurice Norcott, Devendra Sadana
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Patent number: 4344358Abstract: The present invention relates to a processing chamber which is suited for the processing of food, for example meat or meat products, by smoke or steam, comprising at least one unit for the generation of steam and/or smoke and/or for the cleaning of the chamber. The invention consists in that at least one of these units and/or a fan is arranged in the door (1) of the chamber or on the inside or outside of said door.Type: GrantFiled: June 10, 1981Date of Patent: August 17, 1982Inventor: Siegfried Maurer