Patents by Inventor Sigeru Morita

Sigeru Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4746625
    Abstract: A semiconductor manufacturing method which comprises the steps of forming a polycrystalline silicon layer on a semiconductor substrate; depositing a silicon oxide layer on the polycrystalline silicon layer; mounting an acidproof layer on the silicon oxide layer; selectively eliminating the acidproof layer deposited on a semiconductor element-isolating region by the photoetching process; selectively eliminating the silicon oxide layer with the retained acidproof layer used as a mask; ion implanting a channel stopper impurity in the semiconductor substrate through the masks formed of a photoresist coated on the acidproof layer the acidproof layer, and silicon oxide layer; eliminating the photoresist; selectively depositing a silicon layer on the exposed polycrystalline silicon; carrying out thermal oxidation with the acidproof layer used as a mask; eliminating the acidproof layer; filling an oxide in the cavities of the side walls of the semiconductor element-isolating insulation layer; and exposing by etching
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: May 24, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sigeru Morita, Masakazu Kakumu
  • Patent number: 4721687
    Abstract: A method of manufacturing a semiconductor substrate, and, in particular, a technique of electrically isolating a semiconductor element formed on a semiconductor substrate. The method comprises the steps of depositing a silicon oxide layer on the surface of a silicon substrate, for its protection; forming a silicon nitride layer on the silicon oxide layer; selectively eliminating the silicon nitride layer; oxidizing the silicon substrate, with the retained silicon nitride layer being used as a mask, thereby providing an oxide layer; depositing a polycrystalline silicon layer on the oxide layer and the retained acid-resisting layer; oxidizing the polycrystalline silicon layer to provide an insulation layer; eliminating the insulation layer until the silicon nitride layer is exposed; and removing all the silicon nitride layer.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: January 26, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masakazu Kakumu, Sigeru Morita
  • Patent number: 4642881
    Abstract: A method of manufacturing a nonvolatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon dioxide layer is formed by the steps of forming the gate oxide film on a semiconductor element region in a silicon substrate; removing a portion of the gate oxide film to expose a portion of the silicon substrate; implanting impurity ions in the exposed portion of the substrate to an extent that a peak concentration of the impurity ions exceeds a solid solution limit at a temperature of the following thermal annealing step; activating the implanted impurity by thermal annealing so as to form a high impurity concentration layer and thermally oxidizing a surface of the high impurity concentration layer to form the thin silicon dioxide layer.
    Type: Grant
    Filed: May 17, 1985
    Date of Patent: February 17, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naohiro Matsukawa, Sigeru Morita, Hiroshi Nozawa