Patents by Inventor Sigfredo E. Gonzalez Diaz

Sigfredo E. Gonzalez Diaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-side gate over-voltage stress testing
    Patent number: 11624769
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: April 11, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • HIGH-SIDE GATE OVER-VOLTAGE STRESS TESTING
    Publication number: 20220260627
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • High-side gate over-voltage stress testing
    Patent number: 11353494
    Abstract: A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • HIGH-SIDE GATE OVER-VOLTAGE STRESS TESTING
    Publication number: 20200182925
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Application
    Filed: February 17, 2020
    Publication date: June 11, 2020
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • High-side gate over-voltage stress testing
    Patent number: 10613134
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 7, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • HIGH-SIDE GATE OVER-VOLTAGE STRESS TESTING
    Publication number: 20180180661
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen