Patents by Inventor Sihn Choi

Sihn Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6013109
    Abstract: A crack-resistant fabrication method and fabrication apparatus for a semiconductor package prevents interface isolation and cracks by coating a semiconductor chip disposed in a semiconductor package, a paddle of a lead frame, bonding wires and a bond paste using a polyimide type coating material. The coating material forms a coating film to act as a buffering member. The fabrication method can include the steps of attaching a semiconductor chip on a paddle, electrically coupling the semiconductor chip and leads, forming a coating film on the surfaces of the semiconductor chip and the leads, and molding the semiconductor chip, the leads, and the coating film.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: January 11, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventor: Sihn Choi
  • Patent number: 5871782
    Abstract: An improved transfer molding apparatus has a laminated chase block with many sets, which is capable of fabricating a plurality of semiconductor packages. The apparatus includes an upper plate and a movable lower plate and a plurality of posts disposed between the upper and lower plates. A plurality of laminated chase blocks is fixed to the posts. A plurality of ejecting means are disposed at one side of the chase blocks and supply means concurrently supplies a molding compound to the plurality of chase blocks.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: February 16, 1999
    Assignee: LG Semicon Co. Ltd.
    Inventor: Sihn Choi
  • Patent number: 5753857
    Abstract: A charge coupled device (CCD) semiconductor chip package includes a body having a hole formed in the center thereof and a projection extending inwardly from the inner wall of the body. A plurality of outleads are embedded in the projection, and a plate is attached to the upper surface of the projection. A glass lid is attached to the upper surface of the body for covering the upper portion of the hole. A chip has a light receiving area and a plurality of solder balls, and a bottom cover fills the lower portion of the hole and supports the chip. The CCD package chip employs a direct connection technique of outleads to solder balls formed on chip pads, instead of a wire bonding process, which demands a high temperature environment. By using a price competitive plastic body, material cost is reduced compared to a costly material, such as a ceramic body, when fabricating a semiconductor package. Further, package reliability is enhanced.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: May 19, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Sihn Choi
  • Patent number: 5693573
    Abstract: A semiconductor package lead deflash method comprises the steps of forming a plating thin film on a plurality of leads, weakening an adhesive force of the plating thin film, and removing a flash and the plating thin film formed therebeneath respectively from the plurality of leads. The lead deflash method enables complete elimination of the lead flash formed during a package fabrication, and additionally serves as a pollution deterrent by adopting a chemical-free deflash method.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: December 2, 1997
    Assignee: LG Semicon Co., Ltd.
    Inventor: Sihn Choi