Patents by Inventor Silvana Rodrigues

Silvana Rodrigues has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240080122
    Abstract: This application discloses a packet transmission method and apparatus, a device, and a storage medium, and relates to the field of communication technologies. The method includes: in response to that a second slave port of a network device is invalid or the second slave port does not exist, a second master port of the network device obtains a second dataset, where the second dataset is obtained by modifying a first dataset, and the first dataset includes a timestamp carried in a first clock packet received by a first slave port and data generated by the first slave port based on the first clock packet. The network device sends a second clock packet based on the second dataset through the second master port, where a timestamp carried in the second clock packet is the timestamp carried in the first clock packet.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Inventors: Jingfei LYU, Silvana RODRIGUES, Hongliang SU, Hao LI
  • Patent number: 10075284
    Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 11, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Silvana Rodrigues, Michael Rupert, Zaher Baidas, Leon Goldin
  • Patent number: 9852039
    Abstract: An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, and a plurality of PLL-timed physical devices that are identical to the physical devices used in the customer's communication system. A first connector receptacle and a second connector receptacle are coupled to the control logic and to one or more of the PLL-timed physical devices, and are configured to receive a PLL card including a PLL timing device. A third connector receptacle is coupled in series between the first connector receptacle and the second connector receptacle and is configured to receive a backplane emulator card having electrical characteristics emulating a backplane of the customer's communication system.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: December 26, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC
    Inventors: Leon Goldin, Silvana Rodrigues