Patents by Inventor Silvio E. Bou-Ghazale
Silvio E. Bou-Ghazale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies
Patent number: 10268122Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.Type: GrantFiled: July 8, 2014Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Silvio E. Bou-Ghazale, Abhik Ghosh, Niti Goel -
Patent number: 10217732Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.Type: GrantFiled: June 25, 2014Date of Patent: February 26, 2019Assignee: INTEL CORPORATIONInventors: Rany T. Elsayed, Niti Goel, Silvio E. Bou-Ghazale, Randy J. Aksamit
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Patent number: 10026686Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: June 27, 2014Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: Silvio E. Bou-Ghazale, Rany T. Elsayed, Niti Goel
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Publication number: 20170148728Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: June 27, 2014Publication date: May 25, 2017Inventors: Silvio E. BOU-GHAZALE, Rany T. ELSAYED, Niti GOEL
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Publication number: 20170077050Abstract: Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.Type: ApplicationFiled: June 25, 2014Publication date: March 16, 2017Applicant: INTEL CORPORATIONInventors: RANY T. ELSAYED, NITI GOEL, SILVIO E. BOU-GHAZALE, ANSHUMALI ROY, JOSEPH C. YIP
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TECHNIQUES TO ACHIEVE AREA REDUCTION THROUGH CO-OPTIMIZING LOGIC CORE BLOCKS AND MEMORY REDUNDANCIES
Publication number: 20170023863Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.Type: ApplicationFiled: July 8, 2014Publication date: January 26, 2017Applicant: INTEL CORPORATIONInventors: SILVIO E. BOU-GHAZALE, ABHIK GHOSH, NITI GOEL -
Publication number: 20170018543Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.Type: ApplicationFiled: June 25, 2014Publication date: January 19, 2017Applicant: INTEL CORPORATIONInventors: Rany T. ELSAYED, Niti GOEL, Silvio E. BOU-GHAZALE, Randy J. AKSAMIT
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Patent number: 7328415Abstract: An integrated circuit may be divided into blocks and analyzed using a modeling algorithm which facilitates the concurrent analysis of a plurality of blocks forming an integrated circuit. In some cases, an electrical connectivity description of a block may be utilized to create static-timing representations that contain the logic that communicates with the boundary of a block. Once the models for the blocks forming an integrated circuit are generated, static-timing analysis may take place concurrently with all the relevant, identified paths.Type: GrantFiled: February 20, 2001Date of Patent: February 5, 2008Assignee: Intel CorporationInventors: Silvio E. Bou-Ghazale, Cuong M. Le, Michael S. Jones, Timothy J. Fisher
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Publication number: 20020116695Abstract: An integrated circuit may be divided into blocks and analyzed using a modeling algorithm which facilitates the concurrent analysis of a plurality of blocks forming an integrated circuit. In some cases, an electrical connectivity description of a block may be utilized to create static-timing representations that contain the logic that communicates with the boundary of a block. Once the models for the blocks forming an integrated circuit are generated, static-timing analysis may take place concurrently with all the relevant, identified paths.Type: ApplicationFiled: February 20, 2001Publication date: August 22, 2002Inventors: Silvio E. Bou-Ghazale, Cuong M. Le, Michael S. Jones, Timothy J. Fisher