Abstract: A drive circuit includes: an input stage configured to receive a first input signal and a second input signal, and to output a first output signal and a common-mode output signal, where the first input signal and the second input signal are complementary signals; an output stage configured to receive the first output signal, and to output a second output signal; and a duty cycle adjusting subcircuit configured to determine the first output signal and the common-mode output signal or a signal obtained by inverting the common-mode output signal as a control signal, and to adjust a duty cycle of the second output signal. The drive circuit determines the common-mode output signal or the signal obtained by inverting the common-mode output signal as the control signal of the duty cycle adjusting subcircuit, and adjusts the duty cycle of the second output signal to tend to a preset value.

Abstract: A delay locked loop is provide, including a pre-processing module, a first variable delay line and a phase processing module. The pre-processing module is configured to receive an initial clock signal, pre-process the initial clock signal and output a first clock signal. The first variable delay line is configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal. The phase processing module is configured to receive a preset control code and the first target clock signal, perform delay processing on the first target clock signal based on the preset control code, and output at least one delayed target clock signal.

Abstract: A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.

Abstract: Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

Abstract: A signal masking circuit includes a receiving circuit, a delay control circuit, and a logical operation circuit. The receiving circuit is configured to: receive a signal to be processed and a chip select (CS) signal, and output an initial processing signal and an initial CS signal. The delay control circuit is configured to perform delay and logical control operations on the initial CS signal to obtain a CS masking signal, where a pulse width of the CS masking signal is greater than or equal to two preset clock periods. The logical operation circuit is configured to perform invalid masking on the initial processing signal according to the CS masking signal to obtain a target signal.

Abstract: A drive circuit includes: an input stage configured to receive a first input signal and a second input signal, and to output a first output signal and a common-mode output signal, where the first input signal and the second input signal are complementary signals; an output stage configured to receive the first output signal, and to output a second output signal; and a duty cycle adjusting subcircuit configured to determine the first output signal and the common-mode output signal or a signal obtained by inverting the common-mode output signal as a control signal, and to adjust a duty cycle of the second output signal. The drive circuit determines the common-mode output signal or the signal obtained by inverting the common-mode output signal as the control signal of the duty cycle adjusting subcircuit, and adjusts the duty cycle of the second output signal to tend to a preset value.

Abstract: The present disclosure provides a calibration circuit, a memory, and a calibration method. The calibration circuit includes: a calibration resistance module, wherein an output voltage of the calibration resistance module varies with a first parameter, and the first parameter includes at least one of a fabrication process of the calibration circuit, a power supply voltage of the calibration circuit, or an operating temperature of the calibration circuit; a reference voltage generation module, configured to receive a first comparison signal, to generate a corresponding reference voltage; and a comparison module, coupled to the calibration resistance module and the reference voltage generation module, and configured to compare the output voltage with the reference voltage and generate the first comparison signal.

Abstract: A signal masking circuit includes a receiving circuit, a delay control circuit, and a logical operation circuit. The receiving circuit is configured to: receive a signal to be processed and a chip select (CS) signal, and output an initial processing signal and an initial CS signal. The delay control circuit is configured to perform delay and logical control operations on the initial CS signal to obtain a CS masking signal, where a pulse width of the CS masking signal is greater than or equal to two preset clock periods. The logical operation circuit is configured to perform invalid masking on the initial processing signal according to the CS masking signal to obtain a target signal.

Abstract: Embodiments provide an input buffer circuit and a semiconductor memory. a compensation subcircuit is provided between an input terminal of the input buffer circuit and a first terminal of a load subcircuit, a current of an output terminal of the input buffer circuit is increased, and voltage variation of the input terminal can be transmitted to the output terminal in time, such that the output terminal can timely receive the voltage variation of the input terminal, thereby avoiding distortion of an output signal, solving a problem of signal attenuation for the input buffer circuit, improving sensitivity of the input buffer circuit, and preventing negative effects from being caused to transmission of commands inside a system.