Patents by Inventor Simon Andrew Ford
Simon Andrew Ford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10303661Abstract: A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device. A corresponding method of operating a non-volatile mass storage device is provided and a computer program is provided for obtaining the information dependent upon the state of the non-volatile mass storage device, for locally accessing the memory circuitry and for generating the file for storage on the memory circuitry.Type: GrantFiled: June 30, 2016Date of Patent: May 28, 2019Assignee: ARM LimitedInventors: Simon Andrew Ford, Christopher James Styles
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Patent number: 9870230Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.Type: GrantFiled: June 12, 2009Date of Patent: January 16, 2018Assignee: ARM LimitedInventors: Simon Andrew Ford, Stephen John Hill
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Patent number: 9557994Abstract: A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements.Type: GrantFiled: October 14, 2009Date of Patent: January 31, 2017Assignee: ARM LimitedInventors: Dominic Hugo Symes, Simon Andrew Ford
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Publication number: 20160306795Abstract: A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device.Type: ApplicationFiled: June 30, 2016Publication date: October 20, 2016Inventors: Simon Andrew FORD, Christopher James STYLES
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Patent number: 9405939Abstract: A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device. A corresponding method of operating a non-volatile mass storage device is provided and a computer program is provided for obtaining the information dependent upon the state of the non-volatile mass storage device, for locally accessing the memory circuitry and for generating the file for storage on the memory circuitry.Type: GrantFiled: October 7, 2008Date of Patent: August 2, 2016Assignee: ARM LIMITEDInventors: Simon Andrew Ford, Christopher James Styles
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Patent number: 8762744Abstract: A data processing apparatus and methods are disclosed. The data processing apparatus comprises: data processing elements operable to process data; an energy management unit operable to generate energy management information indicative of an energy state of at least one of the data processing elements when processing said data; and logic operable to receive said energy management information and to generate energy management information items associating said energy state with the processing of said data. The information items can provide visibility of how the Energy State of the data processing elements vary in response to the processing of data. Providing this visibility of the Energy State can advantageously enable more detailed the energy management to be performed and the Energy State of the data processing elements to be optimized.Type: GrantFiled: December 6, 2005Date of Patent: June 24, 2014Assignee: ARM LimitedInventors: Simon Andrew Ford, Daryl Wayne Bradley, George James Milne, John Michael Horley
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Patent number: 8675006Abstract: A shared memory is provided accessible by a central processing unit and a graphics processing unit. A bus is provided via which the central processing unit, graphics processing unit and shared memory communicate. A first mechanism controls the graphics processing unit and the central processing unit routes control signals via the bus. An interface is provided between the central processing unit and the graphics processing unit, and an additional mechanism controls the graphics processing unit and the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, and it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.Type: GrantFiled: August 11, 2009Date of Patent: March 18, 2014Assignee: ARM LimitedInventors: Simon Andrew Ford, Sean Tristram Ellis, Edward Charles Plowman
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Patent number: 8621336Abstract: A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations.Type: GrantFiled: August 1, 2008Date of Patent: December 31, 2013Assignee: ARM LimitedInventors: Simon John Craske, Andrew Christopher Rose, Paul Stanley Hughes, Antony John Penton, Richard York, Simon Andrew Ford, Stuart David Biles, Alex James Waugh
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Patent number: 8484508Abstract: A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data.Type: GrantFiled: January 14, 2010Date of Patent: July 9, 2013Assignee: ARM LimitedInventors: Antony John Penton, Simon Andrew Ford, Andrew Christopher Rose
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Patent number: 8250549Abstract: A computer implemented tool is provided for assisting in the mapping of a computer program to a data processing apparatus wherein multiple physical instances of a logical variable in the computer program are required. A computer program is provided as the input to the tool which analyses the data flow of the program and identifies multiple physical instance requirement for logical variables. The tool adds mapping support commands, such as instantiation commands, Direct Memory Access (DMA) move commands and the like as necessary to support the mapping of the computer program to a data processing apparatus.Type: GrantFiled: October 23, 2007Date of Patent: August 21, 2012Assignee: ARM LimitedInventors: Alastair David Reid, Edmund Grimley-Evans, Simon Andrew Ford
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Patent number: 8190807Abstract: A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatus 2 incorporating an asymmetric memory hierarchy formed of a plurality of memories 12, 14. An at least partial architectural description 22, 40 is provided as an input variable to the tool and used to infer missing annotations within a source computer program 24, such as which functions are to be executed by which execution mechanisms 4, 6, 8 and which variables are to be stored within which memories 12, 14. The tool also adds mapping support commands, such as cache flush commands, cache invalidate commands, DMA move commands and the like as necessary to support the mapping of the computer program to the asymmetric multiprocessing apparatus 2.Type: GrantFiled: October 23, 2007Date of Patent: May 29, 2012Assignee: ARM LimitedInventors: Alastair David Reid, Edmund Grimley-Evans, Simon Andrew Ford
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Patent number: 8185724Abstract: An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.Type: GrantFiled: March 3, 2006Date of Patent: May 22, 2012Assignee: ARM LimitedInventors: Simon Andrew Ford, Alastair Reid
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Patent number: 8160861Abstract: The system comprises a component model for modelling aspects of the hardware component, and feature extraction logic for extending the component model to cause the component model, when executing, to output one or more features identifying execution behavior of the component model. A statistical model is then arranged to receive the one or more features output by the component model, and to generate the output dependent on one or more features. The component model may not explicitly model features that can be used to effectively predict values of the observable property, features that a statistical model depends on may still be captured in the underlying logic and implementation of the component model. By extracting features identifying execution behavior of the component model, this can provide a suitable input to the statistical model.Type: GrantFiled: January 14, 2008Date of Patent: April 17, 2012Assignee: ARM LimitedInventors: Simon Andrew Ford, Paul Halliday Peeling
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Publication number: 20110173433Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.Type: ApplicationFiled: June 12, 2009Publication date: July 14, 2011Inventors: Simon Andrew Ford, Stephen John Hill
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Publication number: 20110173482Abstract: A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: ARM LIMITEDInventors: Antony John Penton, Simon Andrew Ford, Andrew Christopher Rose
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Patent number: 7937535Abstract: Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.Type: GrantFiled: February 22, 2007Date of Patent: May 3, 2011Assignee: ARM LimitedInventors: Emre Özer, Stuart David Biles, Simon Andrew Ford
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Patent number: 7840001Abstract: Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer ‘n’ of the groups of data elements over a corresponding ‘n’ processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the ‘n’ of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages.Type: GrantFiled: November 4, 2005Date of Patent: November 23, 2010Assignee: ARM LimitedInventors: Lionel Belnet, Stephane Eric Sebastien Brochier, Simon Andrew Ford
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Patent number: 7809989Abstract: An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10. A master diagnostic unit 26 tracks the migration of thread execution between the different execution mechanisms 6, 8, 10 so that the execution of a given thread can be followed by the diagnostic mechanisms 20, 22, 24, 26 and this information provided to the programmer. The execution mechanisms 6, 8, 10 can be diverse such as a general purpose processor 6, a DMA unit 12, a coprocessor, an VLIW processor, a digital signal processor 8 and a hardware accelerator 10. The asymmetric multiprocessor apparatus 2 will also typically include an asymmetric memory hierarchy such as including two or more of a global memory, a shared memory 16, a private memory 18 and a cache memory 14.Type: GrantFiled: October 18, 2007Date of Patent: October 5, 2010Assignee: ARM LimitedInventors: Simon Andrew Ford, Alastair David Reid, Katherine Elizabeth Kneebone, Edmund Grimley-Evans
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Patent number: 7788417Abstract: A programmer 10 for a target device 16 is provided with a mass storage interface 12 for connecting to a host 2 so as to appear as a mass storage device to the host 2. A target programmer 18 is responsive to an image transferred from the host 2 to the programmer 10 to apply that image to the target device 16.Type: GrantFiled: July 2, 2007Date of Patent: August 31, 2010Assignee: ARM LimitedInventors: Simon Andrew Ford, Christopher James Styles
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Patent number: 7761693Abstract: A data processing apparatus includes a register data store that stores data elements, an instruction decoder that decodes an “arithmetic returning high half” instruction, and a data processor that performs data processing operations controlled by the instruction decoder. In response to the decoded arithmetic returning high half instruction, the data processor specifies within the register data store one or more source registers to store a plurality of source data elements of a first size, and one or more destination registers to store a corresponding plurality of resultant data elements of a second size. The second size is half the size of the first size.Type: GrantFiled: July 13, 2004Date of Patent: July 20, 2010Assignee: ARM LimitedInventors: Dominic Hugo Symes, Simon Andrew Ford