Abstract: A data processing apparatus comprising an integrated circuit 2 having a processor core 4 surrounded by a scan chain 10 is described. The processor core 4 can execute program instructions using either a system clock signal MClk or a test clock signal DClk. A clock selecting bit S within the program instructions for test operation indicates which clock is to be used and a clock selecting mechanism 12, 14 selects the indicated clock signal and passes this to the processor core 4. When the system clock MClk is selected execution of the program instruction by the processor core 4 may be coordinated with the operation of connected auxiliary circuits such as a DRAM 6.

Abstract: The present invention provides a debugger interface unit for a data processing apparatus, comprising a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine. Further, an exception routine catch logic is provided to receive a first signal when a processor core within the data processing apparatus issues an instruction fetch command for an exception routine, and to determine from an instruction address issued with the instruction fetch command which exception routine is being fetched. In addition, the catch logic is arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set, and if the field has been set, to output a breakpoint signal to the processor core.

Abstract: A data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values, each memory location having a corresponding address. The apparatus includes address range storage for storing information identifying address ranges for a plurality of logical regions within said memory, and attribute storage for storing, for each logical region, attributes used to control access to memory locations within said logical region. In accordance with preferred embodiments, one or more of these logical regions may overlap with one another. Further, address comparator logic is provided for comparing an address issued by a processor corresponding to one of said memory locations with the address ranges for said plurality of logical regions, and, if one or more of the logical regions contains said address, for generating a signal indicating those logical regions containing said address.

Abstract: An integrated circuit 2 implementing JTAG debugging and analysis functions has an IDCODE Instruction which returns predetermined data characteristic of the integrated circuit, e.g. manufacturer, part number and version. A portion 20 of the serial test scan chain of the integrated circuit 2 is reused to load and then serially output this identifying data. The serial input of the test and debugging system is connected during such IDCODE Instructions to the start of the portion 20 of the serial test scan chain. This enables the identifying data of a plurality of integrated circuits with linked serial test scan chains to successively output their identifying data in one operation.