Patents by Inventor Simon Cottam
Simon Cottam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220391524Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Ketan Dewan, Trevor Bird, Simon Cottam, Glenn Ashley Farrall, Darren Galpin, Frank Hellwig, Paul Hubbert, Dietmar Koenig, Shubhendu Mahajan, Sandeep Vangipuram
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Publication number: 20200244443Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: Christopher TEMPLE, Simon COTTAM, Frank HELLWIG, Antonio VILELA
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Patent number: 10635615Abstract: A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.Type: GrantFiled: January 25, 2019Date of Patent: April 28, 2020Assignee: Infineon Technologies AGInventors: Simon Cottam, Patrice Woodward
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Patent number: 10637647Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.Type: GrantFiled: April 13, 2017Date of Patent: April 28, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Christopher Temple, Simon Cottam, Frank Hellwig, Antonio Vilela
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Publication number: 20190155775Abstract: A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.Type: ApplicationFiled: January 25, 2019Publication date: May 23, 2019Inventors: Simon Cottam, Patrice Woodward
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Patent number: 10191871Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.Type: GrantFiled: June 20, 2017Date of Patent: January 29, 2019Assignee: Infineon Technologies AGInventors: Simon Cottam, Patrice Woodward
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Publication number: 20180365181Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: Simon Cottam, Patrice Woodward
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Publication number: 20170302441Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.Type: ApplicationFiled: April 13, 2017Publication date: October 19, 2017Inventors: Christopher Temple, Simon Cottam, Frank Hellwig, Antonio Vilela
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Patent number: 9727502Abstract: A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.Type: GrantFiled: July 26, 2013Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Simon Brewerton, Simon Cottam
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Patent number: 9703728Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.Type: GrantFiled: September 23, 2014Date of Patent: July 11, 2017Assignee: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam
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Patent number: 9575912Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.Type: GrantFiled: April 8, 2014Date of Patent: February 21, 2017Assignee: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam, Krishnapriya Chakiat Ramamoorthy
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Patent number: 9569384Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.Type: GrantFiled: March 14, 2013Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam, Harald Zweck
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Publication number: 20150286596Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: Infineon Technologies AGInventors: Frank HELLWIG, Simon COTTAM, Krishnapriya Chakiat RAMAMOORTHY
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Patent number: 9128838Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.Type: GrantFiled: August 2, 2013Date of Patent: September 8, 2015Assignee: Infineon Technologies AGInventors: Antonio Vilela, Simon Cottam
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Patent number: 8996926Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.Type: GrantFiled: October 15, 2012Date of Patent: March 31, 2015Assignee: Infineon Technologies AGInventors: Simon Brewerton, Simon Cottam, Frank Hellwig
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Publication number: 20150089175Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.Type: ApplicationFiled: September 23, 2014Publication date: March 26, 2015Inventors: Frank Hellwig, Simon Cottam
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Publication number: 20150039944Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Antonio Vilela, Simon Cottam
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Publication number: 20150032914Abstract: A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.Type: ApplicationFiled: July 26, 2013Publication date: January 29, 2015Inventors: Simon Brewerton, Simon Cottam
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Publication number: 20140281098Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: Infineon Technologies AGInventors: Frank Hellwig, Simon Cottam, Harald Zweck
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Publication number: 20140108869Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: Infineon Technologies AGInventors: Simon Brewerton, Simon Cottam, Frank Hellwig