Abstract: This disclosure relates to a quantum processor comprising multiple patches of digital qubits and a quantum bus of digital qubits. The quantum bus is configured to connect the multiple patches of digital qubits and to transmit quantum information constituting long-range interactions between the patches of digital qubits. The quantum processor is controlled by a first method of error correction on each of the patches connected by the bus to reduce a relatively high error rate in the digital qubits to a relatively low error rate of each patch, and by a second method of error correction on the multiple patches to correct the relatively low error rate. The number of patches can be increased to increase the distance of the second method and therefore reduce the final error rate. Due to the quantum bus, the patches can be arranged such that there is sufficient space between them for control circuitry.

Abstract: Described herein is a Quantum Computing device comprising a first and a second square patch of qubits, each of the first and second square patch of qubits representing a logical qubit and being in a joint quantum state corresponding to a surface code, the surface code having a distance of two or more. The first and second square patch of qubits have a side-length equal to the distance plus one qubits. The device furthermore comprises one or more chain of qubits prepared in a joint GHZ state serving as a data bus. The chain of qubits neighbors both the first and the second square patch of qubits and has a length equal to or greater than the sum of the two side-lengths.

Abstract: Described herein is a Quantum Computing device comprising a first and a second square patch of qubits, each of the first and second square patch of qubits representing a logical qubit and being in a joint quantum state corresponding to a surface code, the surface code having a distance of two or more. The first and second square patch of qubits have a side-length equal to the distance plus one qubits. The device furthermore comprises one or more chain of qubits prepared in a joint GHZ state serving as a data bus. The chain of qubits neighbors both the first and the second square patch of qubits and has a length equal to or greater than the sum of the two side-lengths.

Abstract: Described herein is a Quantum Computing device comprising a first and a second square patch of qubits, each of the first and second square patch of qubits representing a logical qubit and being in a joint quantum state corresponding to a surface code, the surface code having a distance of two or more. The first and second square patch of qubits have a side-length equal to the distance plus one qubits. The device furthermore comprises one or more chain of qubits prepared in a joint GHZ state serving as a data bus. The chain of qubits neighbors both the first and the second square patch of qubits and has a length equal to or greater than the sum of the two side-lengths.