Abstract: Technologies directed to calibrating phased array antennas are described. A processing device of a communication device causes a first radio to send a first signal via a first antenna element. The first signal has a set of tones. Each tone of the set of tones has a frequency within a fixed frequency range. The processing device causes a second radio to receive a second signal via a second antenna element. The second signal is a response to the first signal. The processing device determines that there is a difference between the second signal and a reference signal. The processing device adjusts at least one of a phase parameter value, a gain parameter value, or a time-delay parameter value of a radio frequency component based on the difference.

Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.

Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.

Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.

Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract: A tuneable E-plane waveguide filter is presented. Tuning is achieved using sliders inserted into the cavities of the insert of the waveguide filter. The sliders are inserted through gaps or notches in the insert, or through notches in the waveguide housing. The positions of the sliders is adjusted to fine-tune the frequency response of the waveguide filter, overcoming limits on narrow relative bandpasses imposed by manufacturing tolerances. When a desired frequency response is achieved, the sliders are fixed in position. Assembly and tuning is less expensive and less complex than tuneable H-plane waveguide filters.