Abstract: The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus.

Abstract: The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.

Abstract: The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.