Abstract: A CMOS dynamic content addressable memory (CAM), having N- and P-channel transistors aligned in stripes for high packing density. In a preferred embodiment, each cell has a four transistor XOR gate for comparing a stored data bit with a comparand bit. Packing density is improved by symmetrically arranging each pair of neighboring rows and each pair of neighboring columns. The device, being of CMOS construction, has an inherently low soft error rate.

Abstract: A quasi content addressable memory circuit including a CAM section, a RAM section, and a comparator. A first part of an incoming comparand is applied to the CAM section, while a second part of the incoming comparand is applied to the comparator. If there is a favorable comparison within the CAM section with the first part of the comparand, the CAM section develops a pointer which addresses the RAM. The output of the RAM is then compared to the second part of the comparand and, if a favorable comparison is made, a match flag is developed. Also disclosed are circuits for handling multiple responses by the CAM section, and a practical comparator RAM which combines the functions of the comparator and the RAM of the quasi content addressable memory circuit.

Abstract: A priority resolution device for bus orientated computer systems. The system includes a plurality of subsystems, each connected to an associated logic circuit, as well as structure for periodically assigning to each of the subsystems together with input to the logic circuit associated therewith a priority indicating an n-bit digital signal. Sets of n signal lines are provided, one set connected to each logic circuit to carry a corresponding bit of the n-bit signal, ranging from the most significant bit (MSB) to the least significant bit (LSB). An open collector bus has n bus lines, each connected to a corresponding one of the signal lines.