Abstract: The invention discloses a method for forming an interfacial passivation layer on the Ge semiconductor. The supercritical CO2 fluids is used to form an interfacial passivation layer between Ge channel and gate insulator layer, and improve the dielectric characteristics of gate insulator after high-temperature thermal annealing process.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: The present invention relates to a light emitting diode with high luminance and method for making the same, and more particularly to a light emitting diode having a transparent window layer which is formed by a semiconductor film of nitrogen-containing compounds. The present invention is mainly directed to growing a window layer of a light emitting diode with a nitrogen-containing compound on the double heterostructure of InGaAlP. Since the energy gap of the nitrogen-containing compound is greater than that of the light emitted from the active layer and is smaller than that of GaP, it is easily to be doped and to form metallic ohmic electrode. Therefore, it is suitable to form a window layer, thereby increasing the light emitting efficiency of a light emitting diode. In addition, the nitrogen-containing compounds can be formed by the current MBE or OMVPE techniques. Therefore, the light emitting diode can be mass-produced and does have industrial applicability.

Abstract: A new method for manufacturing a Group III metal nitride epitaxial wafer comprises providing a first nitrogen-contained gas source, providing a second Group III metal trichloride--containing gas source, and causing said first gas to react with second gas in a heating region, thereby forming a Group III metal nitride epitaxial layer on a substrate. The formed epitaxial wafer can serve as a substrate of a laser diode.

Abstract: A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e.g., IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e.g.

Abstract: Semiconductor crystal films on a dielectric substrate are advantageously made by a zone melting method. Single-crystal structure is initiated at a seed surface, and made to extend across a dielectric surface by melting and resolidifying.Melting is effected upon irradiation with optical radiation which is focused onto an elongated zone; the zone is moved so as to locally melt successive portions of a layer of precursor material which may be amorphous or polycrystalline. The use of incoherent radiation is convenient, and focusing is typically by using a reflector.The process is conveniently effected under a controlled atmosphere and the layer being crystallized may be encapsulated so that no free semiconductor surface is exposed to an atmosphere.

Abstract: One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Abstract: In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).

Abstract: A bipolar transistor NPN structure (20) is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P-type base zone (13.6). Excess acceptor impurities from the polycrystalline silicon electrode (13) are diffused into the base zone (13.6) in order to tailor its conductivity profile.

Abstract: One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Abstract: In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).