Patents by Inventor Simon McElrea
Simon McElrea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220377947Abstract: Systems, methods and apparatus for wireless charging are disclosed. A wireless charging device has a plurality of planar power transmitting coils, a driver circuit and at least one substrate having channels formed therein. The channels can receive a flow of air at a port of entry and conduct the flow of air through the substrate to a port of exit. The planar power transmitting coils may be supported by at least one substrate. Each planar power transmitting coil may be formed as a spiral winding surrounding a power transfer area. The driver circuit may be configured to provide a charging current to one or more of the planar power transmitting coils when a chargeable device is placed on or near the wireless charging device. The one or more channels may be configured to conduct the flow of air past or through the planar power transmitting coils and the driver circuit.Type: ApplicationFiled: May 13, 2022Publication date: November 24, 2022Inventors: Eric Heindel Goodchild, Simon McElrea, Aleksandar Petrovic
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Publication number: 20220311278Abstract: Systems, methods and apparatus for wireless charging are disclosed. A wireless charging device has a plurality of planar power transmitting coils, a coil substrate and a driver circuit. Each planar power transmitting coil may be formed as a spiral winding surrounding a power transfer area. In one example, each planar power transmitting coil is formed by spiral winding a multi-strand wire, each strand in the multistrand wire being electrically insulated from each other strand in the multi-strand wire. The coil substrate may have a plurality of cutouts formed therein. The plurality of cutouts may be configured to secure the planar power transmitting coils in a preconfigured three-dimensional arrangement. The driver circuit may be configured to provide a charging current to one or more of the planar power transmitting coils when a chargeable device is placed on or near the wireless charging device.Type: ApplicationFiled: March 24, 2022Publication date: September 29, 2022Inventors: Eric Heindel Goodchild, Magne Nerheim, Simon McElrea, Aleksandar Petrovic, Mohammad Ali Saket Tokaldani, James Scott
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Publication number: 20150017763Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layerType: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Applicant: INVENSAS CORPORATIONInventors: Belgacem Haba, Simon McElrea
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Patent number: 8912661Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.Type: GrantFiled: November 4, 2010Date of Patent: December 16, 2014Assignee: Invensas CorporationInventors: Scott McGrath, Jeffrey S. Leal, Ravi Shenoy, Loreto Cantillep, Simon McElrea, Suzette K. Pangrle
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Patent number: 8872318Abstract: A microelectronic package includes a subassembly, a second substrate, and a monolithic encapsulant. The subassembly includes a first substrate that has at least one aperture, a coefficient of thermal expansion (CTE) of eight parts per million per degree Celsius or less, and first and second contacts arranged so as to have a pitch of 200 microns or less. First and second microelectronic elements are respectively electrically connected to the first and second contacts. Wire bonds may be used to connect the second element contacts with the second contacts. A second substrate may underlie either the first or the second microelectronic elements and be electrically interconnected with the first substrate. The second substrate may have terminals configured for electrical connection to a component external to the microelectronic package. A monolithic encapsulant may contact the first and second microelectronic elements and the first and second substrates.Type: GrantFiled: August 24, 2011Date of Patent: October 28, 2014Assignee: Tessera, Inc.Inventors: Simon McElrea, Wael Zohni, Belgacem Haba
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Patent number: 8847412Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.Type: GrantFiled: November 9, 2012Date of Patent: September 30, 2014Assignee: Invensas CorporationInventors: Belgacem Haba, Simon McElrea
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Publication number: 20140131900Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layerType: ApplicationFiled: November 9, 2012Publication date: May 15, 2014Applicant: INVENSAS CORPORATIONInventors: Belgacem Haba, Simon McElrea
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Publication number: 20130049196Abstract: A microelectronic package includes a subassembly, a second substrate, and a monolithic encapsulant. The subassembly includes a first substrate that has at least one aperture, a coefficient of thermal expansion (CTE) of eight parts per million per degree Celsius or less, and first and second contacts arranged so as to have a pitch of 200 microns or less. First and second microelectronic elements are respectively electrically connected to the first and second contacts. Wire bonds may be used to connect the second element contacts with the second contacts. A second substrate may underlie either the first or the second microelectronic elements and be electrically interconnected with the first substrate. The second substrate may have terminals configured for electrical connection to a component external to the microelectronic package. A monolithic encapsulant may contact the first and second microelectronic elements and the first and second substrates.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: TESSERA, INC.Inventors: Simon McElrea, Wael Zohni, Belgacem Haba
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Publication number: 20040124534Abstract: Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created entirely of identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.Type: ApplicationFiled: June 12, 2003Publication date: July 1, 2004Inventors: Richard Pommer, Simon McElrea, Brad Banister
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Patent number: 6607939Abstract: Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created entirely of identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.Type: GrantFiled: December 18, 2001Date of Patent: August 19, 2003Assignee: Honeywell International Inc.Inventors: Richard Pommer, Simon McElrea, Brad Banister
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Publication number: 20020092159Abstract: Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created entirely of identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.Type: ApplicationFiled: December 18, 2001Publication date: July 18, 2002Inventors: Richard Pommer, Simon McElrea, Brad Banister
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Patent number: 6388325Abstract: Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created entirely of identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.Type: GrantFiled: November 2, 1999Date of Patent: May 14, 2002Assignee: AlliedSignal Inc.Inventors: Richard Pommer, Simon McElrea, Brad Banister
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Publication number: 20020003303Abstract: Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created entirely of identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.Type: ApplicationFiled: November 2, 1999Publication date: January 10, 2002Inventors: RICHARD POMMER, SIMON MCELREA, BRAD BANISTER