Abstract: An optical see-through (OST) head-mounted display (HMD) uses a calibration matrix having a fixed sub-set of adjustable parameters within all its parameters. Initial values for the calibration matrix are based on a model head. A predefined set of incremental adjustment values is provided for each adjustable parameter. During calibration, the calibration matrix is cycled through its predefined incremental parameter changes, and a virtual object is projected for each incremental change. The resultant projected virtual object is aligned to a reference real object, and the projected virtual object having the best alignment is identified. The setting values of the calibration matrix that resulted in the best aligned virtual object are deemed the final calibration matrix to be used with the OST HMD.

Abstract: An optical see-through (OST) head-mounted display (HMD) uses a calibration matrix having a fixed sub-set of adjustable parameters within all its parameters. Initial values for the calibration matrix are based on a model head. A predefined set of incremental adjustment values is provided for each adjustable parameter. During calibration, the calibration matrix is cycled through its predefined incremental parameter changes, and a virtual object is projected for each incremental change. The resultant projected virtual object is aligned to a reference real object, and the projected virtual object having the best alignment is identified. The setting values of the calibration matrix that resulted in the best aligned virtual object are deemed the final calibration matrix to be used with the OST HMD.

Abstract: A power controller for supplying separately a regulated power source to a plurality of "S" lines and for monitoring line-status conditions on the "S" lines so that each "S" line is controlled independently includes an analog section for delivering power independently to each of the "S" lines and for detecting line-status conditions on the "S" lines. The power controller also includes a microprocessor interface section for communicating with the microprocessor and for controlling the analog section. The analog section is formed of a plurality of output drivers for supplying individually the power to the plurality of "S" lines and line-status detector circuits for sensing line-status conditions on the "S" lines to provide a set of status logic signals for each "S" line. The microprocessor interface section includes an address register for storing a plurality of addresses corresponding to the line-status conditions to be monitored on the "S" lines.

Abstract: A decoder/multiplexer circuit for selecting one of a plurality of input signals includes an array formed of a plurality of decode transistors. All of the collectors of the decode transistors are commonly formed in a large epitaxial pocket, thereby reducing the amount of chip area required.