Patents by Inventor Simon Yang
Simon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6740427Abstract: The invention relates to a ball limiting metallurgy stack for an electrical device that contains a tin diffusion barrier and thermo-mechanical buffer layer disposed upon a refractory metal first layer. The multi-diffusion barrier layer stack resists tin migration toward the upper metallization of the device.Type: GrantFiled: September 21, 2001Date of Patent: May 25, 2004Assignee: Intel CorporationInventors: Madhav Datta, Dave Emory, Tzeun-luh Huang, Subhash M. Joshi, Christine A. King, Zhiyong Ma, Thomas Marieb, Michael Mckeag, Doowon Suh, Simon Yang
-
Patent number: 6593633Abstract: The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.Type: GrantFiled: January 5, 2000Date of Patent: July 15, 2003Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6566727Abstract: A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.Type: GrantFiled: November 3, 1999Date of Patent: May 20, 2003Assignee: Intel CorporationInventors: Reza Arghavani, Robert S. Chau, Simon Yang, John Graham
-
Publication number: 20030059644Abstract: The invention relates to a ball limiting metallurgy stack for an electrical device that contains a tin diffusion barrier and thermo-mechanical buffer layer disposed upon a refractory metal first layer. The multi-diffusion barrier layer stack resists tin migration toward the upper metallization of the device.Type: ApplicationFiled: September 21, 2001Publication date: March 27, 2003Applicant: Intel CorporationInventors: Madhav Datta, Dave Emory, Tzeun-luh Huang, Subhash M. Joshi, Christine A. King, Zhiyong Ma, Thomas Marieb, Michael Mckeag, Doowon Suh, Simon Yang
-
Patent number: 6521964Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: August 30, 1999Date of Patent: February 18, 2003Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6509618Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: January 4, 2000Date of Patent: January 21, 2003Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6506652Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: December 9, 1999Date of Patent: January 14, 2003Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Publication number: 20020082624Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: ApplicationFiled: January 5, 2000Publication date: June 27, 2002Inventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Stephen J. Keating, Alan Myers
-
Publication number: 20020003268Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: ApplicationFiled: January 4, 2000Publication date: January 10, 2002Inventors: CHIA-HONG JAN, JULIE A. TSAI, SIMON YANG, TAHIR GHANI, KEVIN A. WHITEHILL, STEVEN J. KEATING, ALAN MYERS
-
Publication number: 20010045586Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: ApplicationFiled: January 4, 2000Publication date: November 29, 2001Inventors: CHIA-HONG JAN, JULIE A. TSAI, SIMON YANG, TAHIR GHANI, KEVIN A. WHITEHILL, STEVEN J. KEATING, ALAN MYERS
-
Publication number: 20010045607Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with-recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: ApplicationFiled: December 9, 1999Publication date: November 29, 2001Inventors: CHIA-HONG JAN, JULIE A. TSAI, SIMON YANG, TAHIR GHANI, KEVIN A. WHITEHILL, STEVEN J. KEATING, ALAN MYERS
-
Patent number: 6271096Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: December 9, 1999Date of Patent: August 7, 2001Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6268254Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: December 9, 1999Date of Patent: July 31, 2001Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6261925Abstract: A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.Type: GrantFiled: May 8, 1998Date of Patent: July 17, 2001Assignee: Intel CorporationInventors: Reza Arghavani, Robert S. Chau, Simon Yang, John Graham
-
Patent number: 6251762Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;M. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: December 9, 1999Date of Patent: June 26, 2001Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6235598Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: November 13, 1998Date of Patent: May 22, 2001Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 6188117Abstract: A method and device for improved polycide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.Type: GrantFiled: March 25, 1999Date of Patent: February 13, 2001Assignee: Intel CorporationInventors: Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
-
Patent number: 5780346Abstract: A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.Type: GrantFiled: December 31, 1996Date of Patent: July 14, 1998Assignee: Intel CorporationInventors: Reza Arghavani, Robert S. Chau, Simon Yang, John Graham
-
Patent number: 5289035Abstract: A tri-layer titanium coating for an aluminum layer of a semiconductor device. An aluminum layer used for interconnecting individual devices of an integrated circuit is formed on a semiconductor material. A first titanium nitride layer is deposited on the aluminum layer. A titanium layer is deposited on the first titanium nitride layer. A second titanium nitride layer is then deposited on the titanium layer. The tri-layer titanium coating prevents the formation of Al.sub.2 O.sub.3 and AIF.sub.3 during the etching of a via hole in an intermetal dielectric layer deposited above the second titanium nitride layer.Type: GrantFiled: July 15, 1992Date of Patent: February 22, 1994Assignee: Intel CorporationInventors: Melton C. Bost, Simon Yang, Yeochung Yen, Jim Baldo, Barbara Greenebaum
-
Patent number: 5231053Abstract: A tri-layer titanium coating for an aluminum layer of a semiconductor device. An aluminum layer used for interconnecting individual devices of an integrated circuit is formed on a semiconductor material. A first titanium nitride layer is deposited on the aluminum layer. A titanium layer is deposited on the first titanium nitride layer. A second titanium nitride layer is then deposited on the titanium layer. The tri-layer titanium coating prevents the formation of Al.sub.2 O.sub.3 and AlF.sub.3 during the etching of a via hole in an intermetal dielectric layer deposited above the second titanium nitride layer.Type: GrantFiled: October 15, 1991Date of Patent: July 27, 1993Assignee: Intel CorporationInventors: Melton C. Bost, Simon Yang, Yeochung Yen, Jim Baldo, Barbara Greenebaum